Missing label

Sigasi can check the presence of labels, end names, and end labels in the code for all kinds of statements. While labels add a distinctive identity to statements and improve readability, end names and end labels make it easier to determine which declaration or statement is closed when bodies are long or when multiple nested constructs are ending simultaneously.

Example with a small register bank where every statement needs a label, end name, and end label

VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity register_bank is
    port(
        clk      : in  std_logic;
        write    : in  std_logic;
        reg_addr : in  natural;
        reg_load : in  std_logic_vector(7 downto 0);
        reg_out  : out std_logic_vector(7 downto 0)
    );
end entity; -- Missing end name

architecture RTL of register_bank is
    type reg_bank_t is array (15 downto 0) of std_logic_vector(7 downto 0);
    signal reg_bank : reg_bank_t;
begin
    process(clk) is -- Missing label (and end label)
    begin
        if rising_edge(clk) and write = '1' then -- Missing label (and end label)
            reg_bank(reg_addr) <= reg_load;      -- Missing label
        end if;
    end process;

    reg_out <= reg_bank(reg_addr); -- Missing label
end architecture;                  -- Missing end name

VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity register_bank is
    port(
        clk      : in  std_logic;
        write    : in  std_logic;
        reg_addr : in  natural;
        reg_load : in  std_logic_vector(7 downto 0);
        reg_out  : out std_logic_vector(7 downto 0)
    );
end entity register_bank;

architecture RTL of register_bank is
    type reg_bank_t is array (15 downto 0) of std_logic_vector(7 downto 0);
    signal reg_bank : reg_bank_t;
begin
    reg_write : process(clk) is
    begin
        check_clk_write : if rising_edge(clk) and write = '1' then
            write_reg : reg_bank(reg_addr) <= reg_load;
        end if check_clk_write;
    end process reg_write;

    read_reg : reg_out <= reg_bank(reg_addr);
end architecture RTL;

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.

JSONC
{
    "vhdl.rules.251.severity": "{ERROR|WARNING|INFO|IGNORE}",
    "vhdl.rules.251.parameters.entity_end_name": {true|false},
    "vhdl.rules.251.parameters.architecture_end_name": {true|false},
    "vhdl.rules.251.parameters.configuration_end_name": {true|false},
    "vhdl.rules.251.parameters.package_end_name": {true|false},
    "vhdl.rules.251.parameters.package_body_end_name": {true|false},
    "vhdl.rules.251.parameters.context_end_name": {true|false},
    "vhdl.rules.251.parameters.component_end_name": {true|false},
    "vhdl.rules.251.parameters.function_end_name": {true|false},
    "vhdl.rules.251.parameters.procedure_end_name": {true|false},
    "vhdl.rules.251.parameters.record_type_end_name": {true|false},
    "vhdl.rules.251.parameters.physical_type_end_name": {true|false},
    "vhdl.rules.251.parameters.protected_type_end_name": {true|false},
    "vhdl.rules.251.parameters.protected_type_body_end_name": {true|false},
    "vhdl.rules.251.parameters.for_generate_end_label": {true|false},
    "vhdl.rules.251.parameters.if_generate_end_label": {true|false},
    "vhdl.rules.251.parameters.case_generate_end_label": {true|false},
    "vhdl.rules.251.parameters.if_generate_alternative_labels": "{IGNORE|START_LABEL|START_AND_END_LABELS}",
    "vhdl.rules.251.parameters.case_generate_alternative_labels": "{IGNORE|START_LABEL|START_AND_END_LABELS}",
    "vhdl.rules.251.parameters.process_labels": "{IGNORE|START_LABEL|START_AND_END_LABELS}",
    "vhdl.rules.251.parameters.concurrent_block_end_label": {true|false},
    "vhdl.rules.251.parameters.concurrent_procedure_call_label": {true|false},
    "vhdl.rules.251.parameters.concurrent_assertion_label": {true|false},
    "vhdl.rules.251.parameters.concurrent_signal_assignment_label": {true|false},
    "vhdl.rules.251.parameters.if_labels": "{IGNORE|START_LABEL|START_AND_END_LABELS}",
    "vhdl.rules.251.parameters.case_labels": "{IGNORE|START_LABEL|START_AND_END_LABELS}",
    "vhdl.rules.251.parameters.loop_labels": "{IGNORE|START_LABEL|START_AND_END_LABELS}",
    "vhdl.rules.251.parameters.sequential_block_labels": "{IGNORE|START_LABEL|START_AND_END_LABELS}",
    "vhdl.rules.251.parameters.sequential_procedure_call_label": {true|false},
    "vhdl.rules.251.parameters.sequential_assertion_label": {true|false},
    "vhdl.rules.251.parameters.sequential_signal_assignment_label": {true|false},
    "vhdl.rules.251.parameters.variable_assignment_label": {true|false},
    "vhdl.rules.251.parameters.wait_label": {true|false},
    "vhdl.rules.251.parameters.report_label": {true|false},
    "vhdl.rules.251.parameters.next_label": {true|false},
    "vhdl.rules.251.parameters.exit_label": {true|false},
    "vhdl.rules.251.parameters.return_label": {true|false},
    "vhdl.rules.251.parameters.null_label": {true|false}
}

For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:

PREFS
251/severity/${path}={error|warning|info|ignore}
251/params/entity_end_name/${path}={true|false}
251/params/architecture_end_name/${path}={true|false}
251/params/configuration_end_name/${path}={true|false}
251/params/package_end_name/${path}={true|false}
251/params/package_body_end_name/${path}={true|false}
251/params/context_end_name/${path}={true|false}
251/params/component_end_name/${path}={true|false}
251/params/function_end_name/${path}={true|false}
251/params/procedure_end_name/${path}={true|false}
251/params/record_type_end_name/${path}={true|false}
251/params/physical_type_end_name/${path}={true|false}
251/params/protected_type_end_name/${path}={true|false}
251/params/protected_type_body_end_name/${path}={true|false}
251/params/for_generate_end_label/${path}={true|false}
251/params/if_generate_end_label/${path}={true|false}
251/params/case_generate_end_label/${path}={true|false}
251/params/if_generate_alternative_labels/${path}={IGNORE|START_LABEL|START_AND_END_LABELS}
251/params/case_generate_alternative_labels/${path}={IGNORE|START_LABEL|START_AND_END_LABELS}
251/params/process_labels/${path}={IGNORE|START_LABEL|START_AND_END_LABELS}
251/params/concurrent_block_end_label/${path}={true|false}
251/params/concurrent_procedure_call_label/${path}={true|false}
251/params/concurrent_assertion_label/${path}={true|false}
251/params/concurrent_signal_assignment_label/${path}={true|false}
251/params/if_labels/${path}={IGNORE|START_LABEL|START_AND_END_LABELS}
251/params/case_labels/${path}={IGNORE|START_LABEL|START_AND_END_LABELS}
251/params/loop_labels/${path}={IGNORE|START_LABEL|START_AND_END_LABELS}
251/params/sequential_block_labels/${path}={IGNORE|START_LABEL|START_AND_END_LABELS}
251/params/sequential_procedure_call_label/${path}={true|false}
251/params/sequential_assertion_label/${path}={true|false}
251/params/sequential_signal_assignment_label/${path}={true|false}
251/params/variable_assignment_label/${path}={true|false}
251/params/wait_label/${path}={true|false}
251/params/report_label/${path}={true|false}
251/params/next_label/${path}={true|false}
251/params/exit_label/${path}={true|false}
251/params/return_label/${path}={true|false}
251/params/null_label/${path}={true|false}