Sigasi can check that the filename contains the name of at least one of the design unit names inside that file. Note that this check is ignored by default. You can enable it in the VHDL Errors/Warnings settings page ().
Rule configuration
This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.
For Modular Projects, add these entries to your project's
.sigasi/settings.jsonsettings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an@overrideblock; to scope them to a specific target, place them inside a@targetsblock.JSONC{ "vhdl.rules.189.severity": "{ERROR|WARNING|INFO|IGNORE}" }For Classic Projects, add the VHDL lines to
.settings/com.sigasi.hdt.vhdl.linting.prefsand the Verilog/SystemVerilog lines to.settings/com.sigasi.hdt.verilog.linting.prefs:PREFS189/severity/${path}={error|warning|info|ignore}