Dead code linting rule

Dead code is code that does not have any effect on your simulation or synthesis. Examples of dead code are signals that are never used or conditions that are never triggered.

Dead code does not bother the simulator or the synthesis tool. However, it consumes mental energy of anybody reading the code. People will try to figure out the purpose of a given statement and it may take a while before they realize that they are dealing with dead code. This makes it more expensive to review code and reuse code. In general, dead code is a form of technical debt that should be avoided.

Sigasi flags some kinds of dead code:

Unused declarations (signals, constants …):

VHDL
  architecture RTL of empty is
      signal   unused_s : bit;
      constant unused_c : bit := '0';
  begin end;
  

A Quick Fix is available to help you remove unused declarations fast.

Unused ports and generics:

VHDL
  entity empty is
      generic(unused_g : bit);
      port   (unused_p : in bit);
  end entity;
  
  architecture RTL of empty is begin end;
  

Unreachable statements: if the Sigasi analyzer can determine that a condition is always false, it will mark the if-statement because it contains dead code:
VHDL
```
if true then
      v := v + 1;
  else
      v := v - 1;
  end if;
  
```

Dead states in a state machine: a state is considered dead if it has no outgoing transitions:

VHDL
type t_state is (IDLE, START, RUN, DONE);
  signal state: t_state;
    -- [omitted code]
    case state is
      when IDLE   => -- do something
          state <= RUN;
      when RUN    => -- do something
          state <= DONE;
      when DONE   => -- do something
          state <= IDLE;
      when others => -- do nothing
    end case;
  

Rule configuration

These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.

JSONC
{
    "vhdl.rules.55.severity": "{ERROR|WARNING|INFO|IGNORE}", // Unused declaration
    "vhdl.rules.67.severity": "{ERROR|WARNING|INFO|IGNORE}", // Unused ports
    "vhdl.rules.68.severity": "{ERROR|WARNING|INFO|IGNORE}", // Unused generics
    "vhdl.rules.71.severity": "{ERROR|WARNING|INFO|IGNORE}", // Dead states
    "vhdl.rules.79.severity": "{ERROR|WARNING|INFO|IGNORE}"  // Dead code
}

For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:

PREFS
55/severity/${path}={error|warning|info|ignore} # Unused declaration
67/severity/${path}={error|warning|info|ignore} # Unused ports
68/severity/${path}={error|warning|info|ignore} # Unused generics
71/severity/${path}={error|warning|info|ignore} # Dead states
79/severity/${path}={error|warning|info|ignore} # Dead code