Incomplete port maps and generic maps

Sigasi warns about incomplete port maps, generic maps, and parameters in an argument list: Port map uses default values. Missing optional actuals: yourport

Input ports, generics and parameters need to be assigned in your instantiation statement if they don’t already have a default value. If you don’t do this, you are writing illegal VHDL. Sigasi will mark an error, and so will all other tools.

Input ports, generics and parameters with a default value, as well as output ports, do not need to be assigned explicitly. However, this is often not intended. For that reason, Sigasi can warn you about this.

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "vhdl.rules.94.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
94/severity/${path}={error|warning|info|ignore}
```