Unexpected keyword capitalization

VHDL is mostly a case-insensitive language, so keywords can be written in any case: lowercase, uppercase, or any combination of those. Using a consistent casing for keywords throughout the project may improve readability. We recommend synchronizing this setting with the VHDL Lowercase/Uppercase keywords formatting option.

VHDL
signal lower: boolean;
Signal mixed: boolean;
SIGNAL upper: boolean;

This rule can be configured by setting the desired default capitalization: either lowercase, uppercase, or consistent in file. The latter will look at the majority of casing in the file. Some specific keyword capitalization exceptions can also be added.

Note that this rule is set to ignore by default.

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "vhdl.rules.240.severity": "{ERROR|WARNING|INFO|IGNORE}",
    "vhdl.rules.240.parameters.style": "{CONSISTENT_IN_FILE|UPPERCASE|LOWERCASE}",
    "vhdl.rules.240.parameters.overrides": ["${keyword}", ...]
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
240/severity/${path}={error|warning|info|ignore}
240/params/style/${path}={CONSISTENT_IN_FILE|UPPERCASE|LOWERCASE}
240/params/overrides/${path}=[keyword...]
```