Linting rules for loops

Sigasi can check for a number of loop-related problems:

Infinite loop missing a wait (rule 20). Note that infinite while and for loops will not be checked by this rule.

VHDL
process
begin
   loop
      -- statements go here
   end loop;
end process;

process
begin
   loop
      -- statements go here
      wait for 1 ns;
   end loop;
end process;

Empty loop statement (rule 190): the loop body doesn’t contain any statements

VHDL
for loopvar in </span> loop
   -- nothing going on here...
end loop;

for loops that will not execute due to a loop variable with a null range will be flagged with the Null range linting rule.

Rule configuration

These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "vhdl.rules.20.severity": "{ERROR|WARNING|INFO|IGNORE}",
    "vhdl.rules.190.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
20/severity/${path}={error|warning|info|ignore}
190/severity/${path}={error|warning|info|ignore}
```