Naming conventions

See this page for the Verilog equivalent

Naming Conventions allow you to configure patterns to check the correct naming of your identifiers. You can set two patterns for an identifier: a valid pattern that the identifier name must match and an invalid pattern that it must not match. An identifier name is invalid if it matches both patterns or fails to match the valid pattern. Patterns are configured using regex syntax .

Only names with a specified pattern are checked. Empty patterns are omitted.

Example: To enforce a style where all variables have a _v suffix and don’t contain numbers, you would specify .*_v for the valid pattern and .*[0-9].* for the invalid pattern in the Variable name field.

Each pattern field accepts two regular expressions: a valid pattern (the identifier must match) and an invalid pattern (the identifier must not match). For Modular Projects, these are specified as an object { "valid": "...", "invalid": "..." }; either field may be omitted to drop that side of the check. For Classic Projects, the two patterns are joined by a single tab character (omit the tab to specify only a valid pattern, or prefix with a backslash-escaped tab to specify only an invalid pattern).

Rule configuration

These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.

JSONC
{
    "vhdl.rules.92.severity": "{ERROR|WARNING|INFO|IGNORE}",
    "vhdl.rules.92.parameters.alias_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.architecture_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.comment_header": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.concurrent_assignment_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.configuration_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.constant_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.context_declaration": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.entity_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.enumeration_literal_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.file_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.fsm_enumeration_literal_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.fsm_state_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.function_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.generate_statement_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.generic_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.instantiation_statement_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.label": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.package_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.procedure_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.port_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.input_port_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.output_port_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.inout_port_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.process_statement_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.signal_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.type_name": { "valid": "${regex}", "invalid": "${regex}" },
    "vhdl.rules.92.parameters.variable_name": { "valid": "${regex}", "invalid": "${regex}" }
}

For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:

PREFS
92/severity/${path}={error|warning|info|ignore}
92/params/alias_name/${path}=${regex}	${regex}
92/params/architecture_name/${path}=${regex}	${regex}
92/params/comment_header/${path}=${regex}	${regex}
92/params/concurrent_assignment_name/${path}=${regex}	${regex}
92/params/configuration_name/${path}=${regex}	${regex}
92/params/constant_name/${path}=${regex}	${regex}
92/params/context_declaration/${path}=${regex}	${regex}
92/params/entity_name/${path}=${regex}	${regex}
92/params/enumeration_literal_name/${path}=${regex}	${regex}
92/params/file_name/${path}=${regex}	${regex}
92/params/fsm_enumeration_literal_name/${path}=${regex}	${regex}
92/params/fsm_state_name/${path}=${regex}	${regex}
92/params/function_name/${path}=${regex}	${regex}
92/params/generate_statement_name/${path}=${regex}	${regex}
92/params/generic_name/${path}=${regex}	${regex}
92/params/instantiation_statement_name/${path}=${regex}	${regex}
92/params/label/${path}=${regex}	${regex}
92/params/package_name/${path}=${regex}	${regex}
92/params/procedure_name/${path}=${regex}	${regex}
92/params/port_name/${path}=${regex}	${regex}
92/params/input_port_name/${path}=${regex}	${regex}
92/params/output_port_name/${path}=${regex}	${regex}
92/params/inout_port_name/${path}=${regex}	${regex}
92/params/process_statement_name/${path}=${regex}	${regex}
92/params/signal_name/${path}=${regex}	${regex}
92/params/type_name/${path}=${regex}	${regex}
92/params/variable_name/${path}=${regex}	${regex}

Example

A manual configuration where all ports must start with p_ except inout ports, which must start with b_, and where input ports cannot contain numbers. We mark the ports with error markers if they don’t comply.

For a Modular Project, add these entries to your project’s .sigasi/settings.json settings file:

JSONC
{
    "vhdl.rules.92.severity": "ERROR",
    "vhdl.rules.92.parameters.port_name": { "valid": "p_.*" },
    "vhdl.rules.92.parameters.input_port_name": { "invalid": ".*[0-9].*" },
    "vhdl.rules.92.parameters.inout_port_name": { "valid": "b_.*" }
}

For a Classic Project, add these lines to .settings/com.sigasi.hdt.vhdl.linting.prefs:

TEXT
92/severity//<project>=ERROR
92/params/port_name=p_.*
92/params/input_port_name=\	.*[0-9].*
92/params/inout_port_name=b_.*
eclipse.preferences.version=1
isEnabled=true