Redundant "others"

If a case statement contains all the possible choices (usually in an enumerated datatype), you can safely remove the when others clause. Sigasi warns about this:

Unexpected ‘others’ choice, case statement covers all choices explicitly

VHDL
case bits is
  when "00" => -- code
  when "01" => -- code
  when "10" => -- code
  when "11" => -- code
  when others => -- never reached: all cases are covered
end case;

There is some debate on this coding rule. However, the vast majority of synthesis tools do not take the others into account if all choices are enumerated. If the synthesis tool is set up to generate fault-tolerant hardware, the fallback state is the same as the reset state (for most synthesis tools). Check the manual of your synthesis tools and run some experiments. For more information, see VHDL case statements can do without the “others”.

If you still prefer to always have an others choice for case statements, the validation can be configured to Always require 'others' choice. When configured this way, there will be warnings on all case statements that do not have an others choice, even if that choice would be redundant.

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "vhdl.rules.13.severity": "{ERROR|WARNING|INFO|IGNORE}",
    "vhdl.rules.13.parameters.style": "{DISALLOW_REDUNDANT_OTHERS_CHOICES|ALWAYS_REQUIRE_OTHERS_CHOICE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
13/severity/${path}={error|warning|info|ignore}
13/params/style/${path}={DISALLOW_REDUNDANT_OTHERS_CHOICES|ALWAYS_REQUIRE_OTHERS_CHOICE}
```