Signal or variable is never read

Signals and variables that are written but never read are indicative of redundant code, potential logic errors, or inefficiencies in the design. This linting rule detects signals or variables that are never read, as illustrated in the example below.

VHDL
architecture rtl of example is
    signal unread_signal : std_logic;
begin
    process (clk)
    begin
        if rising_edge(clk) then
            unread_signal <= '1'; -- Written, but never read
        end if;
    end process;
end architecture;

VHDL
architecture rtl of example is
begin
    process (clk)
        variable unread_variable : integer := 0;
    begin
        if rising_edge(clk) then
            unread_variable := 42; -- Assigned, but never used
        end if;
    end process;
end architecture;

Note that this rule is set to warning by default.

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "vhdl.rules.89.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
89/severity/${path}={error|warning|info|ignore}
```