The VHDL language reference manual states that:
Every design unit except package STANDARD is assumed to contain the following implicit context items as part of its context clause:
VHDLlibrary STD, WORK; use STD.STANDARD.all;
Hence, any extra library statement in your VHDL code that includes
STD or WORK is pointless, as is any use clause that includes
std.standard.all. Hardly anybody would type the use clause, but
quite some people start all of their files with two extra library
clauses.
It is good practice not to include use clauses for libraries STD and WORK. Sigasi flags a warning if they appear.
library IEEE, STD, WORK;Rule configuration
This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.
For Modular Projects, add these entries to your project's
.sigasi/settings.jsonsettings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an@overrideblock; to scope them to a specific target, place them inside a@targetsblock.JSONC{ "vhdl.rules.49.severity": "{ERROR|WARNING|INFO|IGNORE}" }For Classic Projects, add the VHDL lines to
.settings/com.sigasi.hdt.vhdl.linting.prefsand the Verilog/SystemVerilog lines to.settings/com.sigasi.hdt.verilog.linting.prefs:PREFS49/severity/${path}={error|warning|info|ignore}