Tabs are used

Using tab characters (\t) for indentation or spacing in source files can cause inconsistency in the style of formatting. When enabled, this linting rule reports the use of tab characters.

VHDL
entity example is
	port(
        clk : in std_logic;
        rst : in std_logic
    );
end entity example;

Note that this rule is set to ignore by default.

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "vhdl.rules.99.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
99/severity/${path}={error|warning|info|ignore}
```