Vector width in assignments and port maps

Sigasi checks the vector size in assignments and port maps. This check works at type-time and takes the (symbolic) value of generics into account.

Sigasi will not take into account the value assigned to a generic in instantiations. The reasoning behind this is explained here.

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

• Modular Projects
• Classic Projects

• For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.

  JSONC

  {
      "vhdl.rules.144.severity": "{ERROR|WARNING|INFO|IGNORE}"
  }

• For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:

  PREFS

  144/severity/${path}={error|warning|info|ignore}