Verilog keywords in VHDL

When choosing entity and port names in VHDL, it is recommended not to use (System)Verilog keywords. This will prevent problems if the VHDL entity ever has to be integrated into a mixed VHDL/Verilog project. Sigasi will warn if a (System)Verilog keyword is used as an entity name.

VHDL
entity always is port( -- always is a Verilog keyword: not recommended!

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "vhdl.rules.192.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
192/severity/${path}={error|warning|info|ignore}
```