The target of a signal or variable assignment must be an object that can be written in that context. Sigasi checks the target of every assignment, including each element of an aggregate target, and reports an assignment to an input port, to an input parameter of a subprogram, or to a constant as an error. Such code does not compile, and for ports it usually means the port was declared with the wrong mode or an internal signal was meant instead.
Input port cannot be assigned
A port of mode in can be read but not updated by a signal or variable assignment (LRM 6.5.2). An assignment to it is an error (rule 5), and the message names the port and its mode. A port declared without a mode is an input port too.
entity counter is
port(
clk : in std_logic;
enable : in std_logic;
count : out unsigned(7 downto 0)
);
end entity;
architecture rtl of counter is
begin
enable <= '0'; -- enable is an input port
count <= (others => '0'); -- count is an output port
end architecture;Subprogram parameter cannot be assigned
A signal or variable parameter of mode in cannot be updated either (LRM 6.5.2). Sigasi reports an assignment to such a parameter as an error (rule 6). A parameter declared without a mode is an input parameter.
procedure pulse(signal clk : in std_logic; signal strobe : out std_logic) is
begin
clk <= '1'; -- clk is an input parameter
strobe <= '1'; -- strobe is an output parameter
end procedure;Constant cannot be assigned
A constant has a fixed value once it is elaborated (LRM 6.4.2.2). Only signals or variables can be assigned (rule 7). This covers constants, generics, parameters of class constant, and external names of class constant (LRM 8.7). File parameters cannot be the target of an assignment either.
entity fifo is
generic(DEPTH : natural := 16);
end entity;
architecture rtl of fifo is
constant WIDTH : natural := 8;
begin
process is
variable n : natural;
begin
WIDTH := 16; -- WIDTH is a constant
DEPTH := 32; -- DEPTH is a generic
n := WIDTH * 2; -- n is a variable
wait;
end process;
end architecture;