Clock signal not used as clock

To prevent issues during synthesis or static timing analysis, it’s important to use a signal that is used as a clock exclusively for that purpose, and not as e.g. reset or data. Sigasi will mark all instances where a clock signal is incorrectly used in this manner.

VHDL
p : process (clk) is
    variable data : std_logic_vector(15 downto 0);
begin
    if rising_edge(clk) then
        if rst = '1' then
            ...
        else
            data(8) := clk;
        end if;
    end if;
end process p;

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "vhdl.rules.249.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
249/severity/${path}={error|warning|info|ignore}
```