In a port map or generic map, a formal can be associated with an actual at most once (LRM 6.5.7.2, 6.5.7.3). Sigasi reports named associations whose formal is associated more than once as an error (rule 18).
VHDL
component counter
port(
clk : in std_logic;
reset : in std_logic;
count : out unsigned(7 downto 0)
);
end component;
i_counter : counter port map(
clk => clk,
reset => rst,
clk => clk_b, -- clk is already associated
count => cnt
);
i_counter : counter port map(
clk => clk,
reset => rst,
count => cnt
);
-- Associating the subelements of a composite formal one by one is allowed
i_counter : counter port map(
clk => clk,
reset => rst,
count(7 downto 4) => cnt_high,
count(3 downto 0) => cnt_low
);