Duplicate declaration

VHDL does not allow two declarations with the same name within the same declarative region (LRM 12.3) such as an entity, an architecture, a package, a process, a subprogram. Sigasi reports every repeated declaration as an error (rule 54) and names the first declaration in the message: Duplicate declaration 'count', first declared on line 3, or Duplicate declaration 'count', first declared in file 'pkg.vhd' when the first declaration lives in another file.

VHDL
architecture rtl of counter is
    signal   count : integer;
    constant count : integer := 0;      -- count was already declared on the line above

    type point is record
        x     : integer;
        x     : integer;                -- x was already declared in this record
        count : integer;                -- a nested region hides the outer "count", but is allowed
    end record;
begin
end architecture;

Package and package body

A package and its package body form one declarative region, so a declaration from the package cannot be repeated in the body. However, bodies in the package body for prototypes defined in the package do not count as repetitions:

The body of a subprogram that is declared in the package
The full declaration of a deferred constant, i.e., a constant declared without a value in the package
- However, a constant that already has a value in the package is not deferred and cannot be declared again in the body.

VHDL
package pkg is
    constant depth : integer;           -- deferred constant
    constant width : integer := 8;
    function parity(v : bit_vector) return bit;
end package;

package body pkg is
    constant depth : integer := 16;     -- full declaration of the deferred constant
    constant depth : integer := 32;     -- depth already has a full declaration
    constant depth : integer := 16;     -- width was already fully declared in the package

    function parity(v : bit_vector) return bit is -- body of the function declared in the package
    begin
        return v(v'low);
    end function;

    constant parity : bit := '0';       -- parity was already fully declared in the package
end package body;

The same holds for a protected type and its protected type body.

Enumeration literals

An enumeration literal is actually a parameterless function that returns its enumeration type. Hence, the same literal cannot appear twice in one enumeration type, and a parameterless function that returns the enumeration type cannot have the same name as one of its literals.

VHDL
package states is
    type state is (idle, busy, IDLE);   -- idle was already declared in this type
    type level is ('a', 'A');           -- character literals are case-sensitive

    type colour is (red, green);
    function red return colour;         -- red was already declared as a literal of colour
    function red(v : integer) return colour; -- different parameter type profile, so it overloads the literal
end package;

Subprograms and other overloadable declarations

Subprograms, subprogram instantiations, enumeration literals, and aliases of these are overloadable: several declarations can share one name as long as their signatures differ. The message for a duplicate subprogram shows its signature: Duplicate declaration 'f(x : integer) : integer', first declared on line 2.

VHDL
package pkg is
    function  f(x : integer)    return integer;
    function  f(x : real)       return real;      -- different parameter type
    function  f(x : integer)    return real;      -- different result type
    function  f(x, y : integer) return integer;   -- different number of parameters
    procedure f(x : integer);                     -- a procedure has no result type
    function  f(y : natural) return integer;      -- natural is a subtype of integer
    procedure f(x : out integer);                 -- the mode is not part of the signature
    function  f(x : integer := 0) return integer; -- neither is the default value
end package;

An alias is compared by the signature of the declaration it aliases.

VHDL
package pkg is
    function add(a, b : integer) return integer;
    function add(a, b : real)    return real;
    function sum(a, b : integer) return integer;
    alias plus is add[integer, integer return integer];
    alias plus is add[real, real return real];
    alias add  is sum[integer, integer return integer];  -- "add (a, b : integer) return integer" is already defined on line 2
end package;