Duplicate design units

When multiple files that contain design units with the same names are compiled to the same library, simulators and synthesis tools would use the design unit that is compiled last. However, it might not be a good idea to rely on compilation order in such cases. Thus, Sigasi reports a warning for each duplicate design unit.

print.vhd:

VHDL
  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;

  -- Duplicate design unit 'work.print_result', also declared in file 'out_result.vhd'
  entity print_result is
        port(clock, op : in std_logic;
             result    : in std_logic_vector(31 downto 0));
  end print_result;
  

out_result.vhd:

VHDL
  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;

  -- Duplicate design unit 'work.print_result', also declared in file 'print.vhd'
  entity print_result is
        port(clock, op : in  std_logic;
             fin_res   : out std_logic_vector(31 downto 0);
             result    : in  std_logic_vector(31 downto 0));
  end print_result;
  

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "vhdl.rules.64.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
64/severity/${path}={error|warning|info|ignore}
```