Incomplete reset branch

A reset branch should always reset all registers modified by the corresponding clocked block. An incomplete reset branch could cause unexpected enable or clock gating logic to be synthesized for the registers that were not reset. Sigasi will let you know if a reset branch is incomplete, and what registers are missing.

VHDL
p : process (clk) is
    variable a: integer;
    variable b: integer;
    variable c: integer;
begin
    if rising_edge(clk) then
        if rst = '1' then -- c is not reset
            a := 0;
            b := 0;
        else
            a := a + 1;
            b := b + 2;
            c := c + 3;
        end if;
    end if;
end process p;

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "vhdl.rules.238.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
238/severity/${path}={error|warning|info|ignore}
```