Inconsistent reset style

There are two types of resets for a synchronous design, synchronous resets and asynchronous resets. It can be good practice to consistently use only one of these throughout a project. This rule can be configured to prefer either a synchronous or asynchronous reset style and will mark all reset branches that do not follow the selected style.

For example, if the validation is configured to prefer a synchronous reset style:

VHDL
async_p : process (clk, rst) is
begin
    if rst = '1' then
        ...
    elsif rising_edge(clk) then
        ...
    end if;
end process async_p;

VHDL
sync_p : process (clk) is
begin
    if rising_edge(clk) then
        if rst = '1' then
            ...
        else
            ...
        end if;
    end if;
end process sync_p;

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "vhdl.rules.252.severity": "{ERROR|WARNING|INFO|IGNORE}",
    "vhdl.rules.252.parameters.reset_style": "{ASYNCHRONOUS|SYNCHRONOUS}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
252/severity/${path}={error|warning|info|ignore}
252/params/reset_style/${path}={ASYNCHRONOUS|SYNCHRONOUS}
```