Bitstring contains non-std_logic metavalue

VHDL bit strings include a base specifier followed by a string value. The characters allowed in the value depend on the base specifier, with only a specific set permitted. This linting rule detects string literals that are incorrectly defined. The example below shows an incorrect value, the decimal bit string can only contain numerical characters.

VHDL
entity alu is
    port (
        op     : in  std_logic_vector(3 downto 0) := D"1_1";
        A, B   : in  std_logic_vector(3 downto 0);
        result : out std_logic_vector(3 downto 0)
    );
end alu;

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "vhdl.rules.57.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
57/severity/${path}={error|warning|info|ignore}
```