Multiple objects in one declaration

It is advised not to use multiple-object declarations. It’s better to split declared objects into an equivalent sequence of single-object declarations instead. This practice enhances readability and makes it easier to manage and maintain your code. Sigasi warns the user when multiple objects are declared within a single declaration.

VHDL
entity t is
    generic(
        DATA_WIDTH, ADDR_WIDTH: integer
    );
    port(
        a: in std_logic(DATA_WIDTH - 1 downto 0); -- first operand
        b: in std_logic(DATA_WIDTH - 1 downto 0)  -- second operand
    );
end entity t;

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "vhdl.rules.253.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
253/severity/${path}={error|warning|info|ignore}
```