Superfluous reset

Clocked processes in VHDL are primarily used to describe registers. However, it’s also possible to describe combinational logic in front of these registers. While it is beneficial to reset registers, there is no need to reset signals and variables that describe combinational logic. By default, Sigasi reports superfluous resets in RTL code only.

In the following example, the combinational variable nd is reset together with reg register:

VHDL
inv : process(clk, rst) is
    variable d_reg, nd : std_logic;
begin
    if rst = '1' then
        reg := '0';
        nd  := '0';
    else
        if rising_edge(clk) then
            nd  := not d;
            reg := nd;
        end if;
    end if;
    q <= reg;
end process inv;

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "vhdl.rules.258.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
258/severity/${path}={error|warning|info|ignore}
```