Unbound component instantiation

Omitting explicit bindings for component instantiations in VHDL configurations can introduce ambiguity and errors into your design, making the source code harder to read and maintain. Explicitly binding component instantiations clarifies the intended design hierarchy and helps ensure correct component usage.

This linting rule identifies component instantiations in VHDL configurations that do not have explicit bindings.

VHDL
architecture rtl of processor is
    component alu is
        port (
            op     : in  std_logic_vector(1 downto 0);
            A, B   : in  std_logic_vector(7 downto 0);
            result : out std_logic_vector(7 downto 0)
        );
    end component;
begin
    U1: alu port map (
        op     => op,
        A      => A,
        B      => B,
        result => result
    );
end rtl;

configuration cfg_processor_behavioral of processor is
    for rtl
    end for;
end cfg_processor_behavioral;

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "vhdl.rules.48.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
48/severity/${path}={error|warning|info|ignore}
```