Linting rules for design unit locations

It can be good practice to separate the primary units in a design and declare them in separate files. Similarly, guidelines exist for where secondary units should be declared in relation to other secondary units or to their corresponding primary unit. Sigasi can enforce where design units are defined in relation to other design units.

File contains multiple primary units

Every primary unit should live in a separate file.

VHDL
package pkg1 is
end package;

package pkg2 is    -- more than 1 primary unit in the file
end package;

Secondary unit in unexpected file

Secondary units are more flexible. Sigasi can suggest to put them either in the same file as their corresponding primary unit, or in a separate file (or not check them at all). You can configure this separately for the architecture of entities with a single architecture, for the architectures of an entity with multiple architectures, and for package bodies.

Rule configuration

These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.

JSONC
{
    // Primary unit location
    "vhdl.rules.242.severity": "{ERROR|WARNING|INFO|IGNORE}",
    // Secondary unit location
    "vhdl.rules.243.severity": "{ERROR|WARNING|INFO|IGNORE}",
    "vhdl.rules.243.parameters.single_architecture": "{SAME_FILE_AS_PRIMARY|SEPARATE_FILE|IGNORE}",
    "vhdl.rules.243.parameters.multiple_architectures": "{SEPARATE_FILE|SAME_FILE_AS_PRIMARY|IGNORE}",
    "vhdl.rules.243.parameters.package_body": "{SEPARATE_FILE|SAME_FILE_AS_PRIMARY|IGNORE}"
}

For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:

PREFS
# Primary unit location
242/severity/${path}={error|warning|info|ignore}
# Secondary unit location
243/severity/${path}={error|warning|info|ignore}
243/params/single_architecture/${path}={SAME_FILE_AS_PRIMARY|SEPARATE_FILE|IGNORE}
243/params/multiple_architectures/${path}={SEPARATE_FILE|SAME_FILE_AS_PRIMARY|IGNORE}
243/params/package_body/${path}={SEPARATE_FILE|SAME_FILE_AS_PRIMARY|IGNORE}