Once you have created and populated your Classic Project, you can fine-tune its behavior to match your design requirements. Sigasi offers various configuration options to optimize your development environment:
- Library mapping: Assign HDL files to specific libraries for proper analysis.
- Project settings: Configure project-wide parameters and linting severities.
- Language version: Select the appropriate VHDL or Verilog/SystemVerilog standard for your code.
- SystemVerilog specific configuration: Tweak SystemVerilog-specific settings like include paths and preprocessor defines.
- VHDL specific configuration: Configure VHDL-specific features like code identification, formatting, and conditional variables.
Read on to learn how to configure your project effectively.