VHDL projects in Sigasi support several language-specific configuration options to tailor the design environment to your needs:
- RTL, testbench, and behavioral code identification: Classify your VHDL architectures for specialized analysis.
- VHDL code formatting: Configure project-specific formatting rules for consistent code style.
- VHDL 2019 conditional variables: Define tool directives for conditional code processing.
Read on to learn more about these VHDL-specific features.