VHDL 2019 tool directives provide a streamlined conditional analysis mechanism, similar to the preprocessors found in SystemVerilog or C. These directives allow you to conditionally enable or disable code blocks based on tool type, debug modes, or custom variables.
To configure these variables, right-click your project in the Sigasi Projects View and select Configure > Project Settings. Navigate to VHDL Conditional Variables.
Note: Some keys are reserved and hardcoded as required by the VHDL Language Reference Manual.