Sigasi allows you to define project-specific VHDL formatting settings to ensure a consistent coding style across your team. SystemVerilog and Verilog formatting cannot be configured at this time.
To modify your formatting settings, right-click your project in the Sigasi Projects View and select Configure > Project Settings. Navigate to VHDL Formatting and select Enable project formatting settings.
Properties
- Enable project formatting settings: Specifies whether project-specific formatting settings are active.
- Preserve newlines: The formatter respects existing newlines and will not add or remove them.
- Use vertical alignment: Vertically aligns consecutive declarations and statements (e.g.,
<=or:). - Lowercase/Uppercase keywords: Controls how the formatter transforms keywords:
lowercase,UPPERCASE, orignore. - Alignment column for trailing comments: The column to which trailing comments are aligned. The default is
40; set to0to disable trailing comment alignment.