Manual targets can be used when you want Sigasi to be in the driver seat and be the main source of information on how to build a design. They provide control similar to Classic Projects, but allow specifying everything in a single place, and benefit from the Dependencies mechanism provided by Sigasi Projects. This makes them perfect for projects where a lot of IP is reused.
The following project configuration contains a single manual target with all possible configurable items and their default values.
{
"name": "manual-target",
"targets": {
"hdl": {
"libraryMapping": {
"": []
},
"directory": ".",
"dependencies": [],
"fragment": false,
"ignore": [],
"languageMapping": {
"vhdlSuffix": [
".vhd",
".vhdl"
],
"vhdlVersion": "vhdl-2019",
"verilogSuffix": [
".v"
],
"systemverilogSuffix": [
".sv"
],
"override": {}
},
"verilogPreprocessor": {
"includeDirectories": [],
"define": {},
"multiFileCompilationUnitScope": true
},
"vhdlConditionalAnalysis": {}
}
}
}
The first key is libraryMapping.
It is the only required key for a manual target.
When a new project is created, everything is mapped to the empty list (no libraries).
You can read more on Library mapping in the next part.
The directory key sets the base directory of the target.
Relative paths elsewhere in this target will be resolved from this directory.
By default, the project directory is used.
The dependencies and fragment keys are shared with Scripted targets,
and documented separately on the Dependencies page.
A target fragment will not be validated by itself,
but in context of the targets depending on it.
The ignore list follows a .gitignore pattern format to exclude files from consideration.
The patterns are matched relative to the target’s base directory.
You can use this setting to simplify your library mapping,
or to exclude some very large directories in your project to improve performance.
The languageMapping lets you specify which files are considered Verilog, SystemVerilog or VHDL and,
for the latter, which VHDL version they are written in.
You can configure this for the whole target, and override it for individual files or folders.
The language mapping is most easily configured by right-clicking in the projects view.
Language mapping contains more information on this topic.
Finally, the verilogPreprocessor and vhdlConditionalAnalysis keys configure the Verilog and SystemVerilog preprocessor and VHDL conditional analysis.
You can edit these here manually or use the Target settings graphical configuration page.