When using both Linux and Windows for design development, it’s easy to end up with files that have different end of line sequences:
CRLFin HDL files created on WindowsLFin HDL files created on Linux
You can change the configuration of this rule to enforce a style throughout your Verilog code base. A similar rule exists for VHDL files as well.
Whenever SVH detects a file with line endings that are not allowed by this rule, a corresponding issue is reported. SVH also provides a Quick Fix to change end of line sequences in this file, or in all Verilog files in the project.
Rule Configuration
This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:
172/severity/${path}={error|warning|info|ignore}
172/params/allowed_sequences/${path}={crlf_and_lf|crlf_only|lf_only}