Verilog Empty Assignment Pattern

A SystemVerilog queue or dynamic array can be initialized by using an empty assignment pattern. Though other constructs, such as structs and associative arrays, cannot be initialized this way.

module empty_assignment_pattern;
    int    waiting[$];
    int    clients[];
    string names[int];
    typedef struct { int fruit; } fruit_basket;
    fruit_basket basket;
    
    
    initial begin
        waiting = '{};
        clients = '{};
        names   = '{};
        basket  = '{};
    end
endmodule