Non-blocking assignments are not allowed in functions

A non-blocking assignment (<=) is not allowed in Verilog (2005) functions. SystemVerilog (2017) does allow non-blocking assignments in functions, but only in specific contexts. A function with non-blocking assignments can only be called in initial procedures, always procedures, and in a context where a side effect is allowed. Ensuring these conditions are met is not straightforward. On top of this, they can make the design harder to understand. Sigasi Visual HDL (SVH) flags an error if a non-blocking assignment is used in a Verilog function (rule 41), and can optionally flag a problem for the same issue in SystemVerilog functions (rule 171, disabled by default).

A good fix to correct the problem is to replace non-blocking assignments (<=) with blocking assignments (=)

module badcode;
	function plus_one;
		input integer a;
		begin
			plus_one <= a + 1;  // Incorrect: non-blocking assignment
		end
	endfunction
endmodule

module goodcode;
	function plus_one;
		input integer a;
		begin
			plus_one = a + 1;   // Correct: blocking assignment
		end
	endfunction
endmodule

Rule Configuration

These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured with the following template:

171/severity/${path}={error|warning|info|ignore} # Non-blocking assignments in functions