Verilog Overridden Method Signatures

A virtual method signature should match the overridden method signature in the superclass. Sigasi Visual HDL flags an error if the signatures have a:

• different subroutine form (task or function)
• different return type, if it’s a function
• different arity or any argument with a:
  • different name
  • different direction
  • mismatched type

If an argument default value is present in one method and is missing in the other one, an info message is reported (rule 67).

interface class A;
    pure virtual task who_am_i();
    pure virtual function bit bad(input int a, b, c, d);
    pure virtual task too_bad(input int a, b, c, d);

    pure virtual function A good(input int a, output string b);
endclass

class B implements A;
    virtual function who_am_i();      // should be a task
        // ...
    endfunction

    virtual function logic bad(       // should return bit
        output int a,                 // should be input
        input integer b,              // should be int
        input int si,                 // should be 'c'
        input int d = 4               // should have no default value

    );
        // ...
    endfunction

    virtual task too_bad(ref x, y);   // completely different signature
        // ...
    endtask

    virtual function B good(input int a, output string b);
        // ...
    endfunction
endclass

Rule Configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:

67/severity/${path}={error|warning|info|ignore}