Once you’ve finished a new part of your design, next up is verification. Sigasi supports the entirety of the SystemVerilog—including SystemVerilog assertions—and VHDL grammar and integrates with any library, such as UVM, UVVM, and OSVVM.
Such libraries need a little bit of setup first, though. Sigasi also includes UVM-specific features. Read on to learn all about UVM setup and support.