UVM topology view

Sigasi Visual HDL Professional Edition or Sigasi Visual HDL Enterprise Edition
[Only for SystemVerilog]

The UVM Topology View shows the verification environment’s component topology. When the view is empty, a button is shown that lets you set the root UVM component. This button is also available in the toolbar (). After selecting a root UVM component, the view will be populated with the structure of the selected component and its children, including their ports and virtual interfaces.

As you make changes to the design, the UVM Topology View will automatically refresh.

You can navigate to a topology element in an editor by double-clicking it. Right-clicking an element opens a context menu with more navigation options: you can open the type, declaration, or instantiation of a selected element in an editor.

If you want the selection in the UVM Topology View to follow your position in the editor, make sure to enable Follow Cursor from the More Actions menu. Otherwise, you can explicitly right-click and select Show In > UVM Topology on a UVM component class, a declaration of a component property, an instantiation assignment to this property, or a port connection statement to select the corresponding element in the UVM Topology View.

Buttons in the UVM Topology View

These buttons are available in the UVM Topology View:

• Select Root UVM Component
• Search the UVM Topology View
• Expand all components
• Collapse all components
• More Actions
  • Follow Cursor: links the UVM Topology View with the editor
  • Sort by: Position: sort components, ports, and interfaces by position in the source code
  • Sort by: Name (sort components, ports, and interfaces alphabetically)