Compilation Recipe V2

This page describes the V2 format of the Compilation Recipe. This format is used by the new Sigasi Projects and the Task Automation feature. For the V1 format, used for Eclipse-compatible projects, see the Compilation Recipe V1 documentation.

[Only in Sigasi Visual HDL Enterprise Edition]

The Compilation Recipe Export command provides a standardized, machine-readable way to export the compilation order and all compilation details, such as library mapping and language levels, of your Sigasi project.

The Compilation Recipe V2 format is a JSON file that describes how an HDL project should be compiled. This is a low-level project format that is not intended to be written by users, but rather generated by higher-level tools like Sigasi. The purpose of this format is to have a common and simple format for interoperability between HDL tools like IDEs, simulators, synthesizers, and linters.

How to Generate a V2 Recipe

The Compilation Recipe V2 file is generated by creating an Automated Export task in VS Code. This allows you to automatically generate the recipe whenever your project files change, which is extremely useful for integrating with downstream tools like simulators, linters, or CI/CD pipelines.

For detailed instructions on how to create and configure this task, please refer to the Automated Export of Compilation Recipes section in the Task Automation documentation.

Compilation Recipe Format

The Compilation Recipe V2 format uses a JSON file to describe the compilation steps for an HDL project. The root of this file is an object with the following properties:

Property	Type	Description
`version`	string	The version of the compilation recipe format.
`compilationSteps`	array	An array of objects where each object represents a single compilation step.

Each object in the compilationSteps array must have a compile property that specifies the language to be compiled. Based on this, the object will have different properties.

Shared Properties

All compilation steps share the following properties:

Property	Type	Description
`library`	string	The name of the library into which the files will be compiled.

Verilog/SystemVerilog Compilation

This compilation step is used for Verilog and SystemVerilog files. The compile property must be one of "verilog", "systemverilog", or "verilog/systemverilog".

Property	Type	Default	Description
`compile`	string		Must be one of `"verilog"`, `"systemverilog"`, or `"verilog/systemverilog"`.
`files`	array		An array of files to be compiled. Each item can be a string (file path), an object `{"libraryFile": "path/to/file"}`, or an object `{"moduleSearchPath": "path/to/dir"}`.
`verilogVersion`	string		Optional. The Verilog standard to use. Can be `"verilog-1995"`, `"verilog-2001"`, or `"verilog-2005"`.
`systemVerilogVersion`	string		Optional. The SystemVerilog standard to use. Can be `"systemverilog-2012"`, `"systemverilog-2017"`, or `"systemverilog-2023"`.
`systemVerilogSuffix`	array of strings		If `"compile": "verilog/systemverilog"` is configured. An array of file suffixes (e.g., `[".sv", ".svh"]`) to identify SystemVerilog files.
`visibleLibraries`	array of strings		Optional. A list of other libraries that should be visible during compilation.
`includeDirectories`	array of strings		Optional. A list of directories to be added to the include path.
`directives`	object		Optional. An object containing key-value pairs of directives (e.g., `{"DEBUG": "true"}`).
`moduleSearchFileSuffixes`	array of strings		Optional. An array of file suffixes to search for in the module search paths.
`multiFileCompilationUnitScope`	boolean	`true`	Optional. If `true`, all files in this step are compiled as a single compilation unit.

VHDL Compilation

This compilation step is used for VHDL files. The compile property must be "vhdl".

Property	Type	Description
`compile`	string	Must be `"vhdl"`.
`files`	array of strings	An array of file paths to be compiled.
`vhdlVersion`	string	Optional. The VHDL standard to use. Can be `"vhdl-1987"`, `"vhdl-1993"`, `"vhdl-2002"`, `"vhdl-2008"`, or `"vhdl-2019"`.
`conditionalAnalysis`	object	Optional. An object containing key-value pairs for conditional analysis (e.g., `{"DEBUG": "true"}`).

Examples

Mixed Verilog & SystemVerilog

{
  "compile": "verilog/systemverilog",
  "library": "test",
  "systemVerilogVersion": "systemverilog-2017",
  "verilogVersion": "verilog-2005",
  "systemVerilogSuffix": [".sv", ".svh"],
  "files": [
    "path/to/first.v",
    { "libraryFile": "a/b/libraryFile.v" },
    "path/to/second.sv",
    { "moduleSearchPath" : "path/to/modules" }
  ],
  "includeDirectories": ["include/this/path"],
  "directives": { "DEBUG": "true" }
}

Verilog only

{
  "compile": "verilog",
  "library": "test",
  "verilogVersion": "verilog-2005",
  "files": ["path/to/first.v", "path/to/second.verilog"]
}

SystemVerilog only

{
  "compile": "systemverilog",
  "library": "test",
  "systemVerilogVersion": "systemverilog-2012",
  "files": ["path/to/first.sv", "path/to/second.systemverilog"]
}

VHDL

{
  "compile": "vhdl",
  "library": "test",
  "vhdlVersion": "vhdl-2008",
  "files": ["path/to/a.vhd", "path/to/b.vhd"]
}