You can configure VHDL formatting settings for a project in Sigasi Visual HDL (SVH) to ensure consistent formatting across platforms and among users working on the same project.
Properties
Enable project formatting settings, dictates whether the formatting settings specific to this project are enabledPreserve newlines, the formatter respects newlines: it does not add or remove anyAlign code, align lists such as generics or portsLowercase/Uppercase keywords, controls how the formatter transforms keywords: lowercase, UPPERCASE, or ignoreAlignment column for trailing comments, the column in the line to which the trailing comments will be aligned
