| Empty loops and conditional branches | 1 |
| Check naming conventions | 2 |
| Disallow reg datatype | 3 |
| Named and positional port connections cannot be mixed | 5 |
| The packed keyword is required in packed structs and unions | 6 |
| The module name is a keyword in VHDL and may cause problems in mixed language projects | 7 |
| Case statement does not cover all cases | 8 |
| The for loop statement misses mandatory part (Verilog) | 9 |
| Function prototype has implicit return type | 10 |
| Parameter port list cannot be empty | 11 |
| No semicolon expected at this point (Verilog) | 12 |
| Verilog disallows empty assignments of ordered parameters (Verilog) | 13 |
| Implicit subprogram port direction | 14 |
| Default clause has to be the last item in a case statement | 15 |
| Case statement has multiple default clauses, but only one default clause is allowed | 16 |
| File name does not match design unit | 17 |
| File contains multiple design units | 18 |
| Parameters must have a default value | 19 |
| Verilog code line too long | 20 |
| Tabs are not allowed | 21 |
| File header comment does not match required pattern | 22 |
| Named port connections have to be used for all instances with many ports | 24 |
| Named and positional parameter overrides cannot be mixed | 25 |
| Named parameter overrides have to be used for all instantiations with many parameters | 26 |
| No event control at the top of always construct | 27 |
| Default member must be last in assignment pattern | 28 |
| Only one default member expression is allowed per assignment pattern | 29 |
| Overwritten type key in assignment pattern | 30 |
| Duplicate member key in structure assignment pattern | 31 |
| Mixed named and ordered notation in assignment pattern | 32 |
| Only variable output ports can have a default value in non-ANSI notation | 33 |
| Only input or variable output ports can have a default value in ANSI notation | 34 |
| Register initialization in declarations | 35 |
| Duplicate formal item within the instantiated unit | 37 |
| Missing actuals for formals that have no default value | 38 |
| Excessive number of actuals in ordered notation | 39 |
| Default clause missing from case statement | 40 |
| Non-blocking assignments are not allowed in functions | 41 |
| Consecutive underscores in unit / port identifier | 42 |
| Underscores at end of unit / port identifier | 43 |
| Report encrypted regions | 44 |
| Timing controls are not allowed in functions | 46 |
| Multiple statements per line | 47 |
| Missing bit width for parameters wider than 32 bits | 48 |
| Net data types must be 4-state | 50 |
| Net data types integral | 51 |
| Empty parameters | 53, 54 |
| Invalid package item | 55 |
| Named connections are not allowed with blank ports | 56 |
| Unexpected preprocessor directive inside design elements | 57 |
| Non-packed member in packed structure | 59 |
| Illegal type in untagged union | 60 |
| Illegal class member access | 61 |
| Overridden method signature mismatch | 62-68 |
| Local parameter has to be initialized | 69 |
| Local parameter cannot be overridden | 70 |
| Declaration not found | 71 |
| Attempted implicit declaration with default nettype none | 73 |
| Invalid enumeration element range format | 74 |
| Range of enumeration element is too large | 75 |
| Invalid construct | 76 |
| Invalid randomize argument | 77 |
| Type checking | 78, 79, 94, 100, 131 |
| Constraint class scope missing | 80 |
| Constraint class with packed dimensions | 81 |
| Out-of-bound method signature mismatch | 82-92 |
| Ambiguous reference | 93 |
| Duplicate declaration | 95 |
| Invalid UDP initial value | 96 |
| Implicit net | 97 |
| Duplicate conditions | 98 |
| Upward reference | 99 |
| Duplicate continuous assignments | 101 |
| Different file encoding for including file and included file | 102 |
| Missing macro identifier | 103 |
| Undefined macro | 104 |
| Forbidden macro identifier | 105 |
| Missing `endif | 106 |
| Missing identifier following expansion | 107 |
| Failed include | 108 |
| Macro expansion depth limit reached | 109 |
| Inclusion loop | 110 |
| Issues found while expanding macro | 111 |
| Missing macro argument list | 112 |
| Mismatched number of arguments | 113 |
| Unexpected directive operand | 114 |
| Identifier expansion with an invalid sequence of tokens | 115 |
| Unexpected conditional compiler directive | 116 |
| Whitespace following a backtick | 117 |
| Unknown time literal | 118 |
| Unexpected operand | 119 |
| Missing operand | 120 |
| Invalid preprocessor syntax | 121 |
| Unsupported include path | 122 |
| Syntax error | 123, 124 |
| Invalid macro argument list | 125 |
| Unbalanced expression | 126 |
| Unbalanced directive invocation | 127 |
| Unused macros | 128 |
| Prohibited macro | 129 |
| Unused declaration | 130 |
| Hidden non-virtual methods | 132 |
| Unexpected empty concatenation | 133 |
| Unexpected empty assignment pattern | 134 |
| Incorrect port declaration | 135-139 |
| Duplicate port | 140 |
| Empty port in ANSI port list | 141 |
| Empty port | 142 |
| Vector as edge event expression | 143 |
| Implicit vector to boolean conversion | 144 |
| Missing include path in preprocessor configuration | 155 |
| Unexpected content following directive | 156 |
| End name does not match declaration name | 158 |
| End name not allowed | 159 |
| Duplicate signal in sensitivity list | 160 |
| Cyclic class inheritance | 162 |
| Order of named declaration list does not match | 163 |
| End name without begin name | 164 |
| Mixing statement and block name | 165 |
| Names differing only by case | 166 |
| Deep nesting of conditional and loop statements | 167 |
| Include of globally available declaration | 168 |
| Locally unused port, argument or parameter declaration | 169 |
| Avoid using general purpose ‘always’ | 170 |