Verilog and SystemVerilog Linting

The table below lists the Verilog and SystemVerilog linting rules that SVH can check automatically. The availability of linting rules depends on the license requirements.

Designer Edition Linting Rules

Designer Edition linting rules are available for all editions.

DescriptionID
warningEmpty loops and conditional branches1
warningCheck naming conventions2
ignore with lightbulbDisallow reg datatype3
errorNamed and positional port connections cannot be mixed5
errorThe packed keyword is required in packed structs and unions6
infoThe module name is a keyword in VHDL and may cause problems in mixed language projects7
warningCase statement does not cover all cases8
error with lightbulbThe for loop statement misses mandatory part (Verilog)9
warning with lightbulbFunction prototype has implicit return type10
errorParameter port list cannot be empty11
error with lightbulbNo semicolon expected at this point (Verilog)12
error with lightbulbVerilog disallows empty assignments of ordered parameters (Verilog)13
info with lightbulbImplicit subprogram port direction14
warningDefault clause has to be the last item in a case statement15
errorCase statement has multiple default clauses, but only one default clause is allowed16
warningFile name does not match design unit17
warningFile contains multiple design units18
infoParameters must have a default value19
ignoreVerilog code line too long20
ignoreTabs are not allowed21
ignoreFile header comment does not match required pattern22
warningNamed port connections have to be used for all instances with many ports24
errorNamed and positional parameter overrides cannot be mixed25
warningNamed parameter overrides have to be used for all instantiations with many parameters26
warningNo event control at the top of always construct27
warningDefault member must be last in assignment pattern28
errorOnly one default member expression is allowed per assignment pattern29
warningOverwritten type key in assignment pattern30
errorDuplicate member key in structure assignment pattern31
warningMixed named and ordered notation in assignment pattern32
errorOnly variable output ports can have a default value in non-ANSI notation33
errorOnly input or variable output ports can have a default value in ANSI notation34
warningRegister initialization in declarations35
errorDuplicate formal item within the instantiated unit37
warningMissing actuals for formals that have no default value38
errorExcessive number of actuals in ordered notation39
warningDefault clause missing from case statement40
errorNon-blocking assignments are not allowed in functions41
warningConsecutive underscores in unit / port identifier42
warningUnderscores at end of unit / port identifier43
ignoreReport encrypted regions44
errorTiming controls are not allowed in functions46
warningMultiple statements per line47
warningMissing bit width for parameters wider than 32 bits48
errorNet data types must be 4-state50
errorNet data types integral51
errorEmpty parameters53, 54
errorInvalid package item55
warningNamed connections are not allowed with blank ports56
errorUnexpected preprocessor directive inside design elements57
errorNon-packed member in packed structure59
errorIllegal type in untagged union60
errorIllegal class member access61
errorOverridden method signature mismatch62-68
errorLocal parameter has to be initialized69
errorLocal parameter cannot be overridden70
errorDeclaration not found71
errorAttempted implicit declaration with default nettype none73
errorInvalid enumeration element range format74
errorRange of enumeration element is too large75
errorInvalid construct76
errorInvalid randomize argument77
errorType checking78, 79, 94, 100, 131
errorConstraint class scope missing80
errorConstraint class with packed dimensions81
errorOut-of-bound method signature mismatch82-92
errorAmbiguous reference93
errorDuplicate declaration95
errorInvalid UDP initial value96
warningImplicit net97
warningDuplicate conditions98
warningUpward reference99
warningDuplicate continuous assignments101
errorDifferent file encoding for including file and included file102
errorMissing macro identifier103
errorUndefined macro104
errorForbidden macro identifier105
errorMissing `endif106
errorMissing identifier following expansion107
error with lightbulbFailed include108
errorMacro expansion depth limit reached109
errorInclusion loop110
errorIssues found while expanding macro111
errorMissing macro argument list112
errorMismatched number of arguments113
errorUnexpected directive operand114
errorIdentifier expansion with an invalid sequence of tokens115
errorUnexpected conditional compiler directive116
warningWhitespace following a backtick117
errorUnknown time literal118
errorUnexpected operand119
errorMissing operand120
warningInvalid preprocessor syntax121
errorUnsupported include path122
errorSyntax error123, 124
errorInvalid macro argument list125
errorUnbalanced expression126
errorUnbalanced directive invocation127
warningUnused macros128
ignoreProhibited macro129
warningUnused declaration130
warningHidden non-virtual methods132
errorUnexpected empty concatenation133
errorUnexpected empty assignment pattern134
errorIncorrect port declaration135-139
warningDuplicate port140
errorEmpty port in ANSI port list141
warningEmpty port142
warningVector as edge event expression143
ignoreImplicit vector to boolean conversion144
warning with lightbulbMissing include path in preprocessor configuration155
warningUnexpected content following directive156
error with lightbulbEnd name does not match declaration name158
error with lightbulbEnd name not allowed159
warningDuplicate signal in sensitivity list160
errorCyclic class inheritance162
ignoreOrder of named declaration list does not match163
error with lightbulbEnd name without begin name164
error with lightbulbMixing statement and block name165
ignoreNames differing only by case166
ignoreDeep nesting of conditional and loop statements167
ignoreInclude of globally available declaration168
ignoreLocally unused port, argument or parameter declaration169
warning with lightbulbAvoid using general purpose ‘always’170

UVM Linting Rules

UVM linting rules require a Sigasi Visual HDL Professional Edition or a Sigasi Visual HDL Enterprise Edition license.

You need to explicitly enable UVM linting.

DescriptionID
warningUnregistered UVM object145
warning with lightbulbIncorrect utility macro146
warningType argument value does not match containing class147
warningIncorrect UVM object instantiation148
ignoreUVM object name does not match variable name149
ignoreUnexpected output system task150
warningIncorrect override of UVM object151
warningDeprecated UVM API152
warningUVM phase method does not call superclass method153
warningIncorrect constructor for UVM object or component154

Deprecated Linting Rules

Deprecated linting rules were used by Sigasi at some point, but they’ve been removed or superseded in the most recent version.

DescriptionReasonID
A Verilog net type keyword cannot be followed directly by the reg keywordSuperseded by a syntax error4
Formal item not found within the instantiated unitSuperseded by a syntax error36
Unexpected trailing , in parameter listSuperseded by the Empty parameters rule (rule 53)52
Regular expressions (RE2/J) compatibility checkSuperseded by checks in the preferences58
Ambiguous design unit referenceSuperseded by the more general Ambiguous reference (rule 93)72