VHDL Linting

The table below lists the VHDL linting rules that SVH can check automatically. The availability of linting rules depends on the license requirements.

Designer Edition Linting Rules

Designer Edition linting rules are available for all editions.

	Description	ID
	Null range: The left argument is strictly larger than the right	1
	Positional associations order	2
	‘Others’ position in associations	3
	Multiple others in associations	4
	Input port cannot be assigned	5
	Subprogram parameter cannot be assigned	6
	Constant cannot be assigned	7
	‘others’ has to be the last alternative in a case statement	9
	Deprecated IEEE packages	8
	Only one ‘others’ choice is allowed	10
	Case statement does not cover all cases	11
	Cannot combine ‘others’ with other choices	12
	Consistent use of ‘others’ in case statements	13
	Case alternative contains duplicate choices	14
	C style equality operator	15
	C style inequality operator	16
	Incomplete associations	17
	Duplicate associations	18
	Invalid character literal	19
	Infinite loop. Loop is missing a wait, return or exit statement	20
	Function declarations in a package cannot have a function body	21
	Missing function body	22
	Invalid bit string literal	23
	Null range: The left argument is strictly smaller than the right	26
	Duplicate named associations	27
	Duplicate ‘all’ -style binding for component declaration	28
	Duplicate component instantiation binding	29, 30
	Incorrect number of associations found in mapping	32
	A positional association cannot follow after a named association	33
	A signal cannot be the target of a variable assignment	34
	A port cannot be the target of a variable assignment	35
	A variable cannot be the target of a signal assignment	36
	Non-standard packages	37
	A process must either have a sensitivity list or contain one or more wait statements	38
	A process with a sensitivity list cannot contain any wait statements	39
	Procedure declarations in a package cannot have a procedure body	40
	Procedure declarations in a package body must have a procedure body	41
	Generate statements must have a label	42
	Instantiation statements must have a label	43
	Block statements must have a label	44
	There has to be a whitespace before physical units	47
	Unbound component instantiation	48
	Superfluous library clause	49
	Library is not available	50
	Matching case statement	51
	External name alias	52
	VHDL version check	53
	Duplicate declaration	54
	Find unused declarations	55
	Bitstrings may only contain std_logic metavalues	57
	A unary condition operator parentheses	58
	Duplicate design units	64
	Find unused ports	67
	Find unused generics	68
	Duplicate enum literal	69
	Invalid identifier	70
	Find dead states in state machines	71
	Find incomplete sensitivity lists	72
	Find superfluous signals in sensitivity lists	73
	Function pureness validation	76
	Find dead code	79
	Missing implementation	80
	Incorrect attribute class	81
	Invalid variable assignment	82
	Invalid signal assignment	83
	Encrypted file is used	84
	Find duplicate signals in sensitivity lists	85
	A subprogram call cannot have an empty parameter lis	86
	Detect signals and variables that are never written	88
	Detect signals and variables that are never read	89
	None or multiple matching entities for component	90
	Unexpected tokens	91
	Check naming conventions	92
	Incomplete port map or generic map: using defaults	94
	Check line length	97
	Tabs are used	99
	Array assignment validation	144
	All references must have the same capitalization as their declaration	163
	Check for positional associations in instantiations	164
	Protected type bodies are not allowed in a package	168
	Invalid port associations	169
	VHDL version mismatch	170
	Invalid use of ‘bus’ keyword	171
	Invalid function parameter mode	172
	Invalid variable parameter in function	173
	Invalid function return type	174
	Invalid deferred constant declaration	175
	This declaration is not allowed in the current declarative region	176
	Order of generic and port associations	177
	Name mismatch	178
	Unexpected return type	179
	Configuration issue: Incorrect component name	180
	Configuration issue: Incorrect instantiation statement label	181
	Configuration issue: Missing or incorrect binding indication	182
	Configuration issue: Incorrect name in binding indication	183
	Incorrect use of keyword all	184
	Redundant boolean equality check with true	185
	Boolean equality check with false	186
	Check for component/entity mismatch	187
	Header comment does not match pattern	188
	Filename must contain primary unit name	189
	Empty loop statement	190
	VHDL 87 file declarations	191
	Entity name is a keyword in Verilog and may cause problems in mixed projects	192
	Concatenation of unconstrained aggregate	194
	Empty sensitivity list	197
	Instantiation mismatch	198
	Range wrapped inside parentheses	199
	Incomplete record aggregate	200
	No elements in a list	201
	Trailing separator in a list	202
	Cannot case on a type declaration	209
	Index out of range	210
	Slice has wrong direction	211
	VHDL version check	212
	Invalid use of return type identifiers	213
	Conditional return statements	214
	String literal is not properly closed	215
	An exponent for an integer literal shall not be negative	218
	Declaring the library ‘work’ is not allowed inside a context declaration	219
	Referencing the library ‘work’ is not allowed inside a context declaration	220, 221
	Common Libraries version mismatch	222
	VHDL version check	223
	Check case of non-keywords	224
	Type validation	226
	Loop variables cannot be assigned	227
	Whitespace in extended identifier	228
	Declaration not found	229
	Sequence of operators without parentheses	230
	Constant width vector assigned to signal	231
	Comparison of vectors with different sizes	232
	Missing full constant declaration	233
	Incorrect full constant subtype	234
	Magic number, bitstring, or string in statement	235
	Unconstrained signal or variable of integer type	236
	Unexpected FSM state type	237
	Incomplete reset branch	238
	Deep nesting of conditional and loop statements	239
	Unexpected keyword capitalization	240
	Incorrect vector range direction	241
	File contains multiple primary units	242
	Secondary unit in unexpected file	243
	Prohibited attribute	244
	Prohibited keyword or operator	245
	Prohibited package	246
	Prohibited pragma	247
	Prohibited library	248
	Clock signal not used as clock	249
	Unexpected clock edge specification	250
	Missing label	251
	Inconsistent reset style	252
	Multiple objects in one declaration	253
	Inconsistent clock edge usage	254
	Illegal mode view element mode	256
	Missing mode for record element in mode view	257
	Superfluous reset	258
	Prohibited end of line sequence	260
	Conditional analysis is not standardized for version prior to VHDL 2019

Functional Safety

Mapping of STARC rules to SVH rules and features

Documentation on configuring STARC rules in SVH

STARC rule	Rule name	SVH rules / features
1.1.1.1.	File names should be as follows: `<entity name>.vhd`.	189
1.1.1.2.	Only alphanumeric characters and the underscore `_` should be used, and the first character should be a letter of the alphabet.	92
1.1.1.3.	Do not use reserved words in Verilog (IEEE1364), EDIF, and SDF must not be used.	192 ((System)Verilog only)
1.1.1.4.	Names beginning with `VDD`, `VSS`, `VCC`, `GND` or `VREF` must not be used (uppercase or lowercase).	92
1.1.1.5.	Do not distinguish names by using upper or lower case English letters (Abc, abc).	163
1.1.1.6.	Entity name and component name should be same.	90
1.1.1.9.	At the top level, entity names and port names should consist of 16 or fewer characters and should not be distinguished by upper or lower case alphabet letters.	92
1.1.2.1.	Entity names and instance names should be between 2 and 32 characters in length.	92
1.1.2.5.	Naming conventions for input port names and output port names for each block should be different from those for internal signal names.	92
1.1.3.1.	Naming conventions for internal signal names of blocks should be different from those for input and output ports.	92
1.1.3.3.	Signal names, variable names, type names, label names and function names should be between 2 and 40 characters in length.	92
1.1.4.1.	Use `<name>` + `pac.vhd` for package files	198
1.1.4.2.	For constant declarations, names should start with `C_` or `P_` and all characters of the names should be in upper case letters	92
1.1.6.1.	The architecture name in RTL description should be `RTL`	92
1.1.6.2.	The architecture name in behavior description should be `BEH`	92
1.1.6.3.	The architecture name in test bench description should be `SIM` or `TB`	92
1.1.6.4.	The entity description and RTL architecture description should be made in the same file	243
1.3.1.6.	Do not have both asynchronous reset and synchronous reset on the same reset line	252
1.4.3.1.	Avoid inverting logic on the same clock line. Also avoid using gated clocks and using FFs with different edges.	254
1.4.3.4.	Do not supply clock signals to pins other than FF clock input pins (such as D input)	249
1.4.3.6.	Do not use FFs with inverted edges	254
2.1.2.3.	Specify range when using integer	236
2.1.2.5.	Do not use attribute `enum_encoding`	244
2.1.6.1.	Specification of a range should be `downto`, if it is one-dimensional	211, 241
2.1.8.8.	Do not use procedure in RTL description	245
2.1.9.1.	Use attributes with array; `range`, `length`, `left`, `right`, `high`, `low`, and `reverse_range`	244
2.1.9.2.	Attribute to signal, event, is used for FF inference description	244
2.1.9.3.	Do not infer FF by using `stable`	244
2.1.9.4.	Do not use embedded attributes other than the above	244
2.1.9.5.	Do not use user-defined attributes	244
2.1.10.1.	Do not use `block` statement	245
2.1.10.2.	Do not use `record` type	245
2.1.10.3.	Do not use shared variable	245
2.1.10.4.	Do not use `while` loop	245
2.1.10.5.	Do not use `procedure`	245
2.1.10.6.	Do not use `with -select`	245
2.1.10.7.	Do not use `configuration`	245
2.1.10.8.	Do not use synopsys attribute	245
2.1.10.9.	Do not use access type	245
2.1.10.10.	Do not use `alias`	245
2.1.10.11.	Do not use `bus` and `register`	245
2.1.10.12.	Do not use `disconnect`	245
2.1.10.13.	Do not use `waveform`	245
2.2.1.1.	Latches are generated unless all conditions have been described	11
2.2.2.1.	All signals at the right of the conditional expression and the assignment statement in the process statement of the combinational circuit must be defined in the sensitivity list.	72
2.2.2.2.	Do not define constants and unnecessary signals in the sensitivity list	73
2.2.2.3.	Do not use wait statement in process statement (Sensitivity list is required)	39
2.2.2.4.	he sensitivity list should be verified with a RTL check tool rather than a logic synthesis tool	38, 39, 72, 73, 85, 197
2.3.1.2.	Do not use unsynthesizable FF inference styles	250, 252, 254
2.3.2.2.	Do not use variable in process statement	245
2.3.6.1.	Do not mix FF inferences with and without asynchronous resets in the same process statement	238
2.7.2.2.	Avoid describing conditions that will not be executed	79
2.7.3.1.	The number of nests for if-if and elsif is best at five or less	239
2.7.3.2.	Associating if statements that have deep nesting with else items is difficult	SVH indent guides & code folding
2.7.3.3.	Use of tabs (indenting) will reduce mistakes in if statement nesting	SVH formatting
2.8.1.3.	Avoid the overlapping of case items	14
2.8.1.4.	Always add others choices	13
2.8.3.4.	A syntax error does not occur even if there is no others choice when using integral or enumeration types, however it is better to use others choices	13
2.9.3.1.	Do not use `exit` and `next` in for-loop statement	245
2.10.3.1.	Match the bit width of relational operator	232
3.1.2.1.	Follow the basic naming conventions	92
3.1.3.4.	Define one signal per line in I/O and declaration statement. Always add comments	253 (One declaration per line)
3.1.4.2.	Standardize the number of indents used in process statements, if statements and case statements (two spaces are standard)	SVH formatting
3.1.4.3.	Replace tabs with spaces after editing	99, SVH formatting
3.1.4.5.	The maximum number of characters in one line should be about 110	97
3.2.2.1.	Describe constants by constants as much as possible	235
3.2.3.1.	For component instantiations, connect ports by name connections, not by ordered list	164
3.2.3.2.	Match the bit width of the component port and the bit width of the net to be connected	144
3.3.3.1.	A clock must not be connected to the D input of a FF	249
3.3.6.2.	Do not mix clock lines and reset lines	249
3.5.2.2.	The file name of a RTL description should consist of `<entity name>` + `.vhd`	189
3.5.2.5.	The package file name should be `.vhd` or `_pac.vhd`	SVH file types
3.5.3.1.	Indicate the circuit name, circuit function, author, and creation date in the file header	188
3.5.3.2.	Indicate who made changes and which item was modified in the case of reuse	188
3.5.3.3.	Standardize file headers	188

Mapping of DO-254 rules to SVH rules and features

Documentation on configuring DO-254 rules in SVH

DO-254 rule	Rule name	SVH rules / features
CP1	Avoid Incorrect VHDL Type Usage	144
CP3	Avoid Hard-Coded Numeric Values	235
CP5	Ensure Consistent FSM State Encoding Style	237, 71
CP7	Avoid Mismatching Ranges	1, 26
CP8	Ensure Complete Sensitivity List	72, 73
CP9	Ensure Proper Sub-Program Body	76
CP11	Avoid Unconnected Input Ports	17
CP12	Avoid Unconnected Output Ports	94
CP14	Avoid Unused Declarations	88, 89, 55, 67, 68
SS2	Ensure Proper Case Statement Specification	11, 13, 14
SS7	Avoid Uninitialized VHDL Deferred Constants	175
SS8	Avoid Clock Used as Data	249
SS9	Avoid Shared Clock and Reset Signal	249
SS10	Avoid Gated Clocks	249
SS13	Avoid Mixed Polarity Reset	252
SS21	Ensure Consistent Vector Order	211, 241
DR1	Use Statement Labels	42, 43, 44
DR2	Avoid Mixed Case Naming for Differentiation	163
DR4	Use Separate Declaration Style	253
DR6	Ensure Consistent Indentation	SVH formatting
DR7	Avoid Using Tabs	99
DR10	Ensure Consistent File Header	188
DR13	Ensure Company Specific Naming Standards	92

Deprecated Linting Rules

Deprecated linting rules were used by Sigasi at some point, but they’ve been removed or superseded in the most recent version.

Description	Reason	ID
Invalid generic list	Superseded by 202	24
Invalid generic map	Superseded by 202	25
Duplicate architecture for entity	Superseded by 64	31
Port map lists cannot be terminated with a `,`	Superseded by 202	45
Port lists cannot be terminated with a `,`	Superseded by 202	46
Library is not available	Superseded by checks in the settings	50
Signal declarations are not allowed in a process statement	Superseded by 176	56
End clause validation	Superseded by 51	59
Duplicate entity for library	Superseded by 64	60
Duplicate package for library	Superseded by 64	61
Duplicate configuration for library	Superseded by 64	62
Invalid use clause	Removed as it was invalid	63
Duplicate design unit in IEEE	Removed as it was invalid	65
Find unregistered output ports	Removed as it was invalid	75
Undefined identifier	Superseded by the linker	87
RE2/J compatibility check	Superseded by checks in the settings	225