Meet Our Intern Joran De Decker
Meet Joran, born and raised in Belgium: from dead-end diagrams to a documentation feature he’s proud of
Beyond the prompt
Our next webinar on October 14th is about Agentic Engineering*: when an AI agent starts working an entire engineering objective end to end: planning the steps, choosing which tools to call at each stage, and carrying context from one action into the next.
The Hugging Face incident
What a rogue AI swarm teaches us about writing RTL with agents.
Meet Our Intern Ema Filipovska
This is the first post in a new series where we introduce you to some international students who’ve spent their internship building alongside our engineering team. First up: Ema, Macedonian, who wraps up her time at Sigasi at the end of this month.
Sigasi in Space at BSX India and ESA Industry Days
This September, Sigasi is taking its deterministic HDL platform to two important space industry gatherings: the BSX in India, alongside our Indian distributor Muspark, and the European Industry Space Days at ESA/ESTEC in the Netherlands, hosted by one of our prestiguous customers, the European Space Agency.
Lieven Lemiengre Appointed Chair of the IEEE VHDL Working Group
We’re proud to share that Lieven Lemiengre, VP Product Management at Sigasi, has been appointed Chair of the IEEE P1076 VHDL Analysis and Standardization Group.
AI Can Generate HDL. Can It Finish the Job?
AI coding agents can produce VHDL or SystemVerilog and even remarkably fast. But generating code is only the beginning.
Sigasi Visual HDL 2026.2
AI can generate HDL fast but in professional FPGA and ASIC development, that speed only matters if teams can still understand, validate, and trust what moves downstream. That is what Sigasi 2026.2 is built for.
Sigasi Controls RTL Faster Than AI Can Generate It
AI generates plausible RTL code very fast. But in RTL development, generated code still has to be validated, understood, and reviewed in full project context. No other tool is fast enough to control AI generated code at interactive speed.
Sigasi, your first line of defense
A recent GPTZero investigation should make every engineer pause. They scanned 4,841 accepted NeurIPS 2025 papers and reported 100+ confirmed hallucinated citations spread across 50+ papers; issues that slipped past “3+ reviewers” per paper.
Boost Your Productivity with Sigasi Visual HDL
We’re excited to introduce a new series of short screencasts that show how Sigasi Visual HDL helps FPGA and ASIC engineers work more efficiently—whether you’re writing code from scratch, reusing existing IP, or integrating AI-generated designs.
AI in Chip Design - Webinar
In this webinar, you’ll learn how Sigasi’s approach allows you to safely integrate AI in Chip Design. A must watch for engineers that want to go faster by using AI but don’t want to take the risks associated with AI.
AI in RTL Development
AI assistants and agents can generate RTL fast. But in chip design, generated code still has to be reviewed, validated, and understood in full project context before it can move forward.
Sigasi at Chip Development Symposium
After our second conference of the year in the USA, our team is heading for Europe, where we will be present at the Bavarian Chip Design Center (BCDC) Symposium: “Artificial Intelligence in Chip Design.”
Sigasi Visual HDL 2026.1
This release strengthens what matters most in professional FPGA and ASIC development: fast, deterministic, project-aware feedback — even as designs grow larger and workflows evolve.
