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Sigasi at DAC

2025-06-23

From the early morning in San Francisco we bring you the first picture of DAC 2025! Come and see us to discover our brand new Sigasi Visual HDL 2025.2 and how it will help to save you time and money …

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2025.2 Release

2025-06-20

Transformative state machine improvements The 2025.2 release of our Visual HDL platform brings the focus to your design by enhancing your designing and debugging experience. The all-new Sigasi View …

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11 Myths about IDEs

2025-06-17

ElectronicDesign published an article on the myths about IDEs that have emerged (and need to be debunked) by our VP of Business Development, Dirk Seynhaeve. Let’s be real: The debate over whether …

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Sigasi will be present at the FPGA Conference in Munich

2025-06-16

From Tuesday 1 to Thursday 3 of July, Sigasi will again be at the FPGA Conference, Europe’s leading specialist conference for programmable logic devices, in Munich You are welcome to stop by to …

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Dekimo uses Sigasi to drastically improve productivity and code quality

2025-06-09

Dekimo, a leading independent electronic services supplier in Belgium, the Netherlands, France and Germany, has been using Sigasi for quite some time. We are delighted about that, as customer …

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2025.1 Release

2025-03-20

Additional enhancements with Sigasi Visual HDL 2025.1 The first release of Sigasi Visual HDL in 2025 features various UX improvements, a new VHDL linting rule and improved VHDL highlighting. Sigasi …

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2024.3 Release

2025-01-09

Enjoy the Smoothest Ride with Sigasi Visual HDL 2024.3 Our latest release is all about giving you the smoothest coding experience. With.. improved menus, inline links to diagrams & views, context …

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Sigasi Visual HDL Reviewed in Electronic Engineering

2024-09-30

In September 2024, the Electronic Engineering Journal’s Max Maxfield published a review of Sigasi Visual HDL (SVH). From the Article “So, what’s the big deal—isn’t this just …

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Say Hi to Sigasi Visual HDL 2024.2

2024-09-24

In May 2024, Sigasi announced a new comprehensive portfolio design to help hardware designers and verification engineers catch specification errors earlier in the chip design cycle and fix the …

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Third Installment of System-Level Design "Experts at the Table" Published by Semiconductor Engineering

2024-09-05

Sigasi’s VP for Business Development, Dirk Seynhaeve, joined colleagues from Arteris, Keysight, Siemens EDA, and Synopsys for a round table discussion about the future of system-level design, …

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Sigasi in EE Times on Domain-Specific Computing

2024-08-20

On 15 August 2024, EE Times published an opinion piece by Sigasi CEO Dieter Therssen, about the future of domain-specific computing. From the Article From all accounts, chip design is on a path toward …

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SemiWiki Interviews Sigasi CEO Dieter Therssen

2024-08-19

SemiWiki’s Daniel Nenni interviewed our own CEO Dieter Therssen in the run-up to DAC. You can read his interview at the SemiWiki website .

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Sigasi CEO Weighs in on AI and Domain-Specific Computing

2024-08-16

Semiconductor Engineering’s Brian Bailey put together an intriguing think piece about domain-specific silicon and AI. Throughout, he presents thoughts from industry leaders like Quadric, Blue …

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Sigasi Again Participates in "Experts at the Table" Session hosted by Semiconductor Engineering

2024-08-14

Semiconductor Engineering’s Ann Mutschler once again invited Sigasi’s VP for Business Development, Dirk Seynhaeve  to a session of her popular “Experts at the Table” …

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Second Installment of System-Level Design "Experts at the Table" Published by Semiconductor Engineering

2024-08-14

Sigasi’s VP for Business Development, Dirk Seynhaeve, joined colleagues from Arteris, Keysight, Siemens EDA, and Synopsys for a round table discussion about the future of system-level design, …

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