News
Sigasi at DAC
From the early morning in San Francisco we bring you the first picture of DAC 2025! Come and see us to discover our brand new Sigasi Visual HDL 2025.2 and how it will help to save you time and money …
Read more2025.2 Release
Transformative state machine improvements The 2025.2 release of our Visual HDL platform brings the focus to your design by enhancing your designing and debugging experience. The all-new Sigasi View …
Read more11 Myths about IDEs
ElectronicDesign published an article on the myths about IDEs that have emerged (and need to be debunked) by our VP of Business Development, Dirk Seynhaeve. Let’s be real: The debate over whether …
Read moreSigasi will be present at the FPGA Conference in Munich
From Tuesday 1 to Thursday 3 of July, Sigasi will again be at the FPGA Conference, Europe’s leading specialist conference for programmable logic devices, in Munich You are welcome to stop by to …
Read moreDekimo uses Sigasi to drastically improve productivity and code quality
Dekimo, a leading independent electronic services supplier in Belgium, the Netherlands, France and Germany, has been using Sigasi for quite some time. We are delighted about that, as customer …
Read more2025.1 Release
Additional enhancements with Sigasi Visual HDL 2025.1 The first release of Sigasi Visual HDL in 2025 features various UX improvements, a new VHDL linting rule and improved VHDL highlighting. Sigasi …
Read more2024.3 Release
Enjoy the Smoothest Ride with Sigasi Visual HDL 2024.3 Our latest release is all about giving you the smoothest coding experience. With.. improved menus, inline links to diagrams & views, context …
Read moreSigasi Visual HDL Reviewed in Electronic Engineering
In September 2024, the Electronic Engineering Journal’s Max Maxfield published a review of Sigasi Visual HDL (SVH). From the Article “So, what’s the big deal—isn’t this just …
Read moreSay Hi to Sigasi Visual HDL 2024.2
In May 2024, Sigasi announced a new comprehensive portfolio design to help hardware designers and verification engineers catch specification errors earlier in the chip design cycle and fix the …
Read moreThird Installment of System-Level Design "Experts at the Table" Published by Semiconductor Engineering
Sigasi’s VP for Business Development, Dirk Seynhaeve, joined colleagues from Arteris, Keysight, Siemens EDA, and Synopsys for a round table discussion about the future of system-level design, …
Read moreSigasi in EE Times on Domain-Specific Computing
On 15 August 2024, EE Times published an opinion piece by Sigasi CEO Dieter Therssen, about the future of domain-specific computing. From the Article From all accounts, chip design is on a path toward …
Read moreSemiWiki Interviews Sigasi CEO Dieter Therssen
SemiWiki’s Daniel Nenni interviewed our own CEO Dieter Therssen in the run-up to DAC. You can read his interview at the SemiWiki website .
Read moreSigasi CEO Weighs in on AI and Domain-Specific Computing
Semiconductor Engineering’s Brian Bailey put together an intriguing think piece about domain-specific silicon and AI. Throughout, he presents thoughts from industry leaders like Quadric, Blue …
Read moreSigasi Again Participates in "Experts at the Table" Session hosted by Semiconductor Engineering
Semiconductor Engineering’s Ann Mutschler once again invited Sigasi’s VP for Business Development, Dirk Seynhaeve to a session of her popular “Experts at the Table” …
Read moreSecond Installment of System-Level Design "Experts at the Table" Published by Semiconductor Engineering
Sigasi’s VP for Business Development, Dirk Seynhaeve, joined colleagues from Arteris, Keysight, Siemens EDA, and Synopsys for a round table discussion about the future of system-level design, …
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