Milestone update: Sigasi on the VS Code Marketplace

20,000 downloads

Less than one year ago, we wrote about Sigasi Visual HDL passing 10,000 downloads on the VS Code Marketplace. It had taken Sigasi Studio, our previous IDE, more than three years to reach 9,000 installs. Visual HDL got past 10,000 in 15 months. This time it took less than a year.

The curve, in three numbers

Lined up, the three milestones tell a clearer story than any single number does:

300/month

Sigasi Studio: 9,000 installs in 3 years

600/month

Sigasi Visual HDL, first 10,000: >15 months from launch on June 19, 2024 to September 29, 2025

900/month

Sigasi Visual HDL, next 10,000: <12 months from September 29, 2025 to today

That’s not just continued growth — it’s growth that keeps compressing. Each milestone has taken meaningfully less time than the one before it, on a product that’s now in its second full year rather than its first. For an engineering tool built for a discipline as deliberate and switching-averse as FPGA and ASIC design, that curve is the part we’re proudest of.

What’s changed since 10,000

The product moved fast in the same window the download and install count did. Sigasi Visual HDL 2026.2 shipped Modular Projects — a more reproducible, scriptable way to set up targets, dependencies, and toolchain alignment — alongside MCP integration for VS Code Copilot and Cursor, a rewritten AI-ready CLI with daemon support, Vivado and VUnit import, improved dependency analysis, and enhanced FSM visualization. 2026.3 followed with a focused release for Verilog and SystemVerilog teams, including Verible integration.

We don’t think that’s a coincidence, and we don’t think it’s the whole story either. More teams are bringing coding agents into VHDL, Verilog, and SystemVerilog projects than a year ago, and more of them are discovering that an agent still needs to be grounded in the real project — its libraries, hierarchy, dependencies, and compile order — to be useful on anything beyond a toy example. Some of the growth is engineers finding Sigasi the way they always have: through better linting, navigation, and project understanding on their own FPGA and ASIC work. Some of it is teams looking for a deterministic layer to sit alongside whichever coding agent they’ve adopted.

It also became clear that Sigasi’s ultrafast compiler that can check code while the agent generates it, has become a real asset for teams. This is the moment Sigasi’s interactive speed stops being a novelty and starts being the point. An engine that can give deterministic, project-aware feedback faster than a person can type is exactly the engine you want checking an agent that writes RTL faster than a person can read it. The same semantic model, the same rules, the same diagnostics — just aimed at a much faster source of code. More on this in the next blog, for now we just want to say:

Thank you 🧡

Every one of these downloads is an engineer or a team deciding it was worth the time to try. That’s the actual milestone — not the count itself, but what it represents about how many people are now navigating, reviewing, and validating VHDL, Verilog, and SystemVerilog projects with Sigasi Visual HDL day to day. Thank you for that.

If you haven’t tried it yet, download the free for non-commercial use Community Edition: from the VS Code marketplace , or from our download page. You can also request a trial license for professional use. We will give you a free project setup session on top so you don’t have to figure it out by yourself.

Sigasi, the trusted execution layer for AI-driven RTL development

Agentic Engineering

Join Sigasi’s live webinar on October 14 to see how AI agents use deterministic, project-aware HDL analysis to move from generated code toward review and simulation. Two live demos: • From requirements to an HDL project—and what Sigasi finds after the agent says “done.” • From an existing codebase to a simulation workflow.

For FPGA and ASIC design and verification engineers.

2026-09-26