AI in Chip Design
Sigasi at Chip Development Symposium
After our second conference of the year in the USA, our team is heading for Europe, where we will be present at the Bavarian Chip Design Center (BCDC) Symposium: “Artificial Intelligence in Chip Design.”
Artificial intelligence is rapidly transforming many aspects of semiconductor development, including the tools engineers use to design and verify chips. On March 25, 2026, experts from industry and research will gather at Fraunhofer IIS in Erlangen, Germany, for the 4th Conference on Chip Development, organized by the Bavarian Chip Design Center (BCDC) in cooperation with the Bavarian Chips Alliance.
Sigasi is proud to be part of this event. Sebastian Zarnekow, Product Portfolio Architect at Sigasi, will present a talk titled: “AI-Assisted HDL: What Works, What Breaks, and How to Control Risk.”
We would like to thank our customer Fraunhofer IIS, Institute for Integrated Circuits, for the invitation and for hosting this event that brings together experts from across the semiconductor ecosystem to discuss the role of AI in chip design.
A conference focused on AI in chip design
This year’s conference centers on the theme “Artificial Intelligence in Chip Design.” The program features keynote talks, industry presentations, and real-world case studies on how AI can support the IC design process.
During the morning sessions, leading EDA vendors will present AI-supported design tools and their potential benefits, including productivity improvements and new approaches to chip development.
In the afternoon, speakers from industry will share practical experiences using AI in real chip design projects, discussing measurable efficiency gains and the impact on development workflows.
The event brings together developers, EDA providers, researchers, and semiconductor companies to explore how intelligent tooling can reshape the design flow and accelerate innovation in the semiconductor ecosystem.
Sigasi talk: AI-Assisted HDL in practice
While AI is increasingly integrated into development tools, applying it effectively in hardware design remains a challenge. In his presentation, Sebastian Zarnekow will explore the practical realities of AI-assisted HDL development, focusing on three key questions:
What actually works today? Where AI tools can genuinely improve HDL productivity.
Where does it break down? Common pitfalls such as hallucinations, incorrect code generation, and limitations of current models.
How can teams control risk? Strategies for integrating AI into HDL workflows while maintaining code quality, correctness, and design reliability.
The talk draws on Sigasi’s experience developing advanced language tooling for hardware designers and working closely with engineering teams adopting AI-assisted workflows.
Join the conversation
The conference will run from 10:00 to 16:45 on March 25, 2026, followed by a networking get-together where participants can exchange ideas and connect with peers from across the semiconductor ecosystem.
Participation is free of charge, but registration is required.
If you plan to attend, we would love to meet you there. And if you’re interested in AI-assisted HDL development, don’t miss Sebastian’s session.
Meet the experts
To schedule a meeting, contact our team in advance.
2026-03-04, last modified on 2026-03-16