Lieven Lemiengre Appointed Chair of the IEEE VHDL Working Group
We’re proud to share that Lieven Lemiengre, VP Product Management at Sigasi, has been appointed Chair of the IEEE P1076 VHDL Analysis and Standardization Group.
The IEEE P1076 Working Group is responsible for the continued development and standardization of VHDL. For Sigasi, the appointment is a meaningful recognition of Lieven’s long-standing involvement with VHDL and the broader hardware-design community.
Helping shape the future of VHDL
VHDL remains an important language for professional FPGA and ASIC development, particularly in complex and long-lived engineering environments.
The IEEE P1076 Working Group develops the language standard that defines VHDL’s syntax and semantics and supports its continued evolution. IEEE describes VHDL as a formal notation used throughout the creation of electronic systems, including design, verification, synthesis, testing, communication of design data, and maintenance.
The role of Working Group Chair is not simply ceremonial. IEEE describes the chair as having an important role in guiding working-group discussions toward consensus as standards are developed.
Lieven has been involved in the VHDL community for many years. His contributions to the development of VHDL can be found in the P1076 working materials going back to the work that led to VHDL-2019, and he has regularly shared developments in the language with the wider engineering community.
Standards matter more as development changes
Hardware development is entering a period of rapid change.
Coding agents can now generate and modify HDL increasingly quickly. But professional engineering still depends on exact language semantics, reproducible project understanding, disciplined review, and standards that tools and engineers can rely on.
That makes strong standards no less important in the AI era — arguably, they become even more important.
At Sigasi, we believe AI-assisted development works best when probabilistic generation is combined with deterministic engineering knowledge. Sigasi Visual HDL provides semantic project intelligence for VHDL, Verilog, SystemVerilog, and mixed-language FPGA and ASIC projects, helping engineers and their chosen coding agents work with the actual structure and semantics of the project.
Standards such as IEEE VHDL provide an essential foundation for that deterministic understanding.
Deep language expertise at the heart of Sigasi
Lieven’s appointment also reflects something that has always been central to Sigasi: deep understanding of hardware description languages rather than treating HDL simply as text.
Sigasi builds a semantic model of a complete project, including hierarchy, types, scopes, interfaces, libraries, dependencies and compilation order. That engineering depth is what allows Sigasi Visual HDL to provide real-time project-aware diagnostics, navigation, visualization and deterministic analysis for engineers — and increasingly to expose the same project intelligence to coding agents and automation.
Having Sigasi engineers actively involved in the standards community helps us stay close to the language, the engineers using it, and the challenges facing professional HDL development.
Congratulations, Lieven
We’re delighted to see Lieven take on this responsibility and look forward to his contribution to the continued evolution of VHDL.
Congratulations, Lieven — and thank you to everyone in the P1076 community who contributes their expertise and time to keeping VHDL moving forward.
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2026-08-18