12,000 Downloads and Counting
It took us more than one year to get to 10,000 downloads. In less than 2 months, 2,000 more downloads were done. Our mission to empower design and verification engineers to save time and costs for their team/company pays off.
Verification Frameworks - Webinar on demand
On January 28th we presented our first webinar in 2026, in which we showed how Sigasi’s shift-left approach saves you valuable time and money in verification. A must watch for design & verification engineers in both SystemVerilog and VHDL.
Google Antigravity meets Sigasi
When Google launched Gemini 3 this week, also Antigravity was launched, an agentic development platform, evolving the IDE into the agent-first era. That got our attention and our VP Operations, Mark Christiaens had a first look at it.
From Pioneers to Navigators
In the heart of Silicon Valley, our VP of Business Development, is paving the way for Sigasi in the ASIC world. When we asked Dirk to introduce our Linting Webinar to the American participants, he came up with his exciting story.
10,000 Downloads and Counting
One year ago, we introduced Sigasi® Visual HDL™ on the VS Code Marketplace. Our goal was clear: empower design and verification engineers to write faster, higher-quality RTL code and save time and costs for their team/company.
Introducing Linting In Chip Design Flow
In complex ASIC and FPGA designs, quality cannot be postponed to simulation. Issues introduced during RTL design cause bloating verification cycles, consuming costly engineering time, and risking expensive silicon re-spins.
PRIVATECH Inc. announces partnership with Sigasi® in Japan
Tokyo, Japan / Ghent, Belgium – August 8th, 2025
Privatech announces the distribution of Sigasi® Visual HDL™ which empowers hardware design engineers to reduce development time, decrease costs, improve quality and achieve overall excellence in HDL creation, integration, validation and organization.
Sigasi at DVCON Japan, FPGA Horizons UK and SEMICON Europa
We are in full preparation of a busy end of year season!
On August 20th, Sigasi will be at the DVCon Japan conference in Tokyo together with our new distributor which will be announced very soon.
Muspark Technologies Pvt. Ltd. announces the distribution of Sigasi®
Bangalore, India / Ghent, Belgium - July 10th, 2025
Muspark Technologies announces the distribution of Sigasi® which empowers hardware design and verification engineers to reduce development time, decrease costs, improve quality and achieve overall excellence in HDL creation, integration, validation and organization.
G3TEK Embedded Technologies expands its product offering by distributing Sigasi®
Ankara, Türkiye / Ghent, Belgium - July 9th, 2025
G3TEK Embedded Technologies and Sigasi announce the start of their distribution agreement in Türkiye. Sigasi Visual HDL empowers hardware design and verification engineers to reduce development time, decrease costs, improve quality, and achieve overall excellence in HDL creation, integration, validation, and organization.
Sigasi at FPGA Conference
From Tuesday 1st to Thursday 3rd of July, Sigasi will again be at the FPGA Conference in Munich, Europe’s leading specialist conference for programmable logic devices.
Sigasi at DAC
Come and see us at DAC to discover our brand new Sigasi Visual HDL 2025.2 and how it will help to save you time and money in your next chip design!
2025.2 Release
Transformative state machine improvements
The 2025.2 release of our Visual HDL platform brings the focus to your design by enhancing your designing and debugging experience.
11 Myths about IDEs
ElectronicDesign published an article on the myths about IDEs that have emerged (and need to be debunked) by our VP of Business Development, Dirk Seynhaeve.
Let’s be real: The debate over whether hardware designers and verification engineers need an integrated development environment (IDE) isn’t just a passing trend—it’s an ongoing conversation. Some swear by their trusty text editors, while others can’t imagine working without the bells and whistles of a modern IDE.
2025.1 Release
Additional enhancements with Sigasi Visual HDL 2025.1
The first release of Sigasi Visual HDL in 2025 features various UX improvements, a new VHDL linting rule and improved VHDL highlighting.
