News
Sigasi streamlines VHDL and Verilog development at Socomate
Socomate International is providing both conventional and phased array UT electronics for automated inspections systems. Based near Paris, Socomate has been providing Ultrasonic instrumentation to research, academic and Industrial users since 1977.
2025.1 Release
Additional enhancements with Sigasi Visual HDL 2025.1
The first release of Sigasi Visual HDL in 2025 features various UX improvements, a new VHDL linting rule and improved VHDL highlighting.
2024.3 Release
Enjoy the Smoothest Ride with Sigasi Visual HDL 2024.3
Our latest release is all about giving you the smoothest coding experience. With..
Sigasi Visual HDL Reviewed in Electronic Engineering
In September 2024, the Electronic Engineering Journal’s Max Maxfield published a review of Sigasi Visual HDL (SVH).
Say Hi to Sigasi Visual HDL 2024.2
In May 2024, Sigasi announced a new comprehensive portfolio design to help hardware designers and verification engineers catch specification errors earlier in the chip design cycle and fix the inefficient HDL-based design flow. That portfolio, Sigasi® Visual HDL™ (SVH™), began with the 2024.1 release. Now it’s time for SVH 2024.2.
Third Installment of System-Level Design "Experts at the Table" Published by Semiconductor Engineering
Sigasi’s VP for Business Development, Dirk Seynhaeve, joined colleagues from Arteris, Keysight, Siemens EDA, and Synopsys for a round table discussion about the future of system-level design, hosted by Semiconductor Engineering.
Sigasi in EE Times on Domain-Specific Computing
On 15 August 2024, EE Times published an opinion piece by Sigasi CEO Dieter Therssen, about the future of domain-specific computing.
SemiWiki Interviews Sigasi CEO Dieter Therssen
SemiWiki’s Daniel Nenni interviewed our own CEO Dieter Therssen in the run-up to DAC.
You can read his interview at the SemiWiki website .
Sigasi CEO Weighs in on AI and Domain-Specific Computing
Semiconductor Engineering’s Brian Bailey put together an intriguing think piece about domain-specific silicon and AI. Throughout, he presents thoughts from industry leaders like Quadric, Blue Cheetah, Arteris, Keysight, Siemens EDA, Expedera, Mythic, and Ansys. And also Sigasi: “When it comes to software tasks like LLMs, they will become dominant enough to force new hardware architectures, but won’t stop differentiation all together, not in the short term,” says Dieter Therssen, CEO of Sigasi. “Even the customization of RISC-V is based on the need to do some CNN or LLM processing. A key factor here will be how AI is deployed. Currently, there are so many ways to do so that imaging convergence is still too far out.”
Sigasi Again Participates in "Experts at the Table" Session hosted by Semiconductor Engineering
Semiconductor Engineering’s Ann Mutschler once again invited Sigasi’s VP for Business Development, Dirk Seynhaeve to a session of her popular “Experts at the Table” series. This time he was joined by Michal Siwinski, chief marketing officer at Arteris; Chris Mueth, new opportunities business manager at Keysight; Neil Hand, director of marketing at Siemens EDA; and Frank Schirrmeister, executive director, strategic programs, systems solutions at Synopsys. They discussed how, as chip complexity rises with disaggregation and chiplets, the design process will become increasingly more workflow- and workload-specific.
Second Installment of System-Level Design "Experts at the Table" Published by Semiconductor Engineering
Sigasi’s VP for Business Development, Dirk Seynhaeve, joined colleagues from Arteris, Keysight, Siemens EDA, and Synopsys for a round table discussion about the future of system-level design, hosted by Semiconductor Engineering.
Sigasi joins the EE Journal Fish Fry
Sigasi’s CEO Dieter Therssen and Marketing Manager Jane Judge talked to Amelia Dalton during DAC 2024.
Fish Fry Podcast
EE Journal’s Amelia Dalton breaks down each week’s EE news in an informative, fun, and engaging style in her weekly podcast “Fish Fry.” In June, she sat down with Jane and Dieter during DAC 2024. They talked all things Sigasi, trends in front end chip design, why the shift-left methodology is a game changer for chip designers.
Sigasi Highlighted in Electronics Weekly
During DAC61 , held at the end of June 2024, Caroline Hayes of Electronics Weekly spoke with Sigasi’s Dirk Seynhaeve, about how the new Sigasi® Visual HDL™ seeks to optimize the HDL workflow.
Sigasi Visual HDL 2024.1 Is Here
In May 2024, Sigasi announced a new comprehensive portfolio design to help hardware designers and verification engineers catch specification errors earlier in the chip design cycle and fix the inefficient HDL-based design flow. That portfolio, Sigasi® Visual HDL™ (SVH™) is now available to download from the VS Code marketplace!
Introducing Sigasi Visual HDL
Sigasi Redefines Chip Design Creation, Integration, Validation Leveraging Shift-Left Principles
We’re thrilled to announce the rollout of a comprehensive portfolio developed to catch specification errors early in the chip design cycle and fix the inefficient HDL-based design flow.
