News
PRIVATECH Inc. announces partnership with Sigasi® in Japan
Tokyo, Japan / Ghent, Belgium – August 8th, 2025
Privatech announces the distribution of Sigasi® Visual HDL™ which empowers hardware design engineers to reduce development time, decrease costs, improve quality and achieve overall excellence in HDL creation, integration, validation and organization.
Sigasi at DVCON Japan, FPGA Horizons UK and SEMICON Europa
We are in full preparation of a busy end of year season!
On August 20th, Sigasi will be at the DVCon Japan conference in Tokyo together with our new distributor which will be announced very soon.
Muspark Technologies Pvt. Ltd. announces the distribution of Sigasi®
Bangalore, India / Ghent, Belgium - July 10th, 2025
Muspark Technologies announces the distribution of Sigasi® which empowers hardware design and verification engineers to reduce development time, decrease costs, improve quality and achieve overall excellence in HDL creation, integration, validation and organization.
G3TEK Embedded Technologies expands its product offering by distributing Sigasi®
Ankara, Türkiye / Ghent, Belgium - July 9th, 2025
G3TEK Embedded Technologies and Sigasi announce the start of their distribution agreement in Türkiye. Sigasi Visual HDL empowers hardware design and verification engineers to reduce development time, decrease costs, improve quality, and achieve overall excellence in HDL creation, integration, validation, and organization.
Sigasi makes programming much easier at Zimmer
From traditional screen-printing systems to cutting-edge digital textile and carpet printing technology, ZIMMER AUSTRIA has been at the forefront of innovation since its inception more than 150 years ago. With expertise in coating and finishing solutions, dryers, loop steamers, and auxiliary equipment, ZIMMER AUSTRIA offers a comprehensive range of solutions to meet the evolving needs of the industry.
Sigasi at FPGA Conference
From Tuesday 1st to Thursday 3rd of July, Sigasi will again be at the FPGA Conference in Munich, Europe’s leading specialist conference for programmable logic devices.
Sigasi at DAC
Come and see us at DAC to discover our brand new Sigasi Visual HDL 2025.2 and how it will help to save you time and money in your next chip design!
2025.2 Release
Transformative state machine improvements
The 2025.2 release of our Visual HDL platform brings the focus to your design by enhancing your designing and debugging experience.
11 Myths about IDEs
ElectronicDesign published an article on the myths about IDEs that have emerged (and need to be debunked) by our VP of Business Development, Dirk Seynhaeve.
Let’s be real: The debate over whether hardware designers and verification engineers need an integrated development environment (IDE) isn’t just a passing trend—it’s an ongoing conversation. Some swear by their trusty text editors, while others can’t imagine working without the bells and whistles of a modern IDE.
Dekimo uses Sigasi to drastically improve productivity and code quality
Dekimo, a leading independent electronic services supplier in Belgium, the Netherlands, France and Germany, has been using Sigasi for quite some time. We are delighted about that, as customer satisfaction is their most important achievement.
Sigasi streamlines VHDL and Verilog development at Socomate
Socomate International is providing both conventional and phased array UT electronics for automated inspections systems. Based near Paris, Socomate has been providing Ultrasonic instrumentation to research, academic and Industrial users since 1977.
2025.1 Release
Additional enhancements with Sigasi Visual HDL 2025.1
The first release of Sigasi Visual HDL in 2025 features various UX improvements, a new VHDL linting rule and improved VHDL highlighting.
2024.3 Release
Enjoy the Smoothest Ride with Sigasi Visual HDL 2024.3
Our latest release is all about giving you the smoothest coding experience. With..
Sigasi Visual HDL Reviewed in Electronic Engineering
In September 2024, the Electronic Engineering Journal’s Max Maxfield published a review of Sigasi Visual HDL (SVH).
Say Hi to Sigasi Visual HDL 2024.2
In May 2024, Sigasi announced a new comprehensive portfolio design to help hardware designers and verification engineers catch specification errors earlier in the chip design cycle and fix the inefficient HDL-based design flow. That portfolio, Sigasi® Visual HDL™ (SVH™), began with the 2024.1 release. Now it’s time for SVH 2024.2.
