News
Sigasi Again Participates in "Experts at the Table" Session hosted by Semiconductor Engineering
Semiconductor Engineering’s Ann Mutschler once again invited Sigasi’s VP for Business Development, Dirk Seynhaeve to a session of her popular “Experts at the Table” … (more ...)
Second Installment of System-Level Design "Experts at the Table" Published by Semiconductor Engineering
Sigasi’s VP for Business Development, Dirk Seynhaeve, joined colleagues from Arteris, Keysight, Siemens EDA, and Synopsys for a round table discussion about the future of system-level design, … (more ...)
Sigasi joins the EE Journal Fish Fry
Sigasi’s CEO Dieter Therssen and Marketing Manager Jane Judge talked to Amelia Dalton during DAC 2024. Fish Fry Podcast EE Journal’s Amelia Dalton breaks down each week’s … (more ...)
Sigasi Highlighted in Electronics Weekly
During DAC61 , held at the end of June 2024, Caroline Hayes of Electronics Weekly spoke with Sigasi’s Dirk Seynhaeve, about how the new Sigasi® Visual HDL™ seeks to optimize the HDL … (more ...)
Sigasi Visual HDL 2024.1 Is Here
In May 2024, Sigasi announced a new comprehensive portfolio design to help hardware designers and verification engineers catch specification errors earlier in the chip design cycle and fix the … (more ...)
Introducing Sigasi Visual HDL
Sigasi Redefines Chip Design Creation, Integration, Validation Leveraging Shift-Left Principles We’re thrilled to announce the rollout of a comprehensive portfolio developed to catch … (more ...)
Second Installment of "Experts at the Table" Published by Semiconductor Engineering
Sigasi’s VP for Business Development, Dirk Seynhaeve, joined colleagues from Axiomise, Cadence, Siemens EDA, and Synopsys for a round table discussion about finding and eliminating bugs in HDL … (more ...)
Sigasi Unveils a New Look and Feel
We’re delighted to announce our new look and feel, including a new logo Our new logo design puts our core business front and center: improving HDL development. The modernized outline text of … (more ...)
Sigasi takes part in "Experts at the Table" hosted by Semiconductor Engineering
Sigasi’s VP for Business Development, Dirk Seynhaeve, took part in a titilating discussion recently hosted by Semiconductor Engineering. The topic at hand: Finding and eliminating bugs at the … (more ...)
Say Hello to Sigasi 5.5
UVM has arrived and VS Code keeps getting better Today, we’re delighted to release Sigasi 5.5—which brings UVM to the stage and adds our most-loved features to our VS Code extension—but this is … (more ...)
Welcome to Sigasi 5.4
Better VS Code Experience, Better Linting We’re happy to bring you Sigasi 5.4, which brings you new UVM linting rules simpler linting rule configuration in Eclipse diagrams and documentation … (more ...)
Sigasi 5.3 is here!
More control for you, more supported linting rules The Sigasi Studio 5.3 release does the following: includes many new VHDL linting rules, many of which improve support for designing toward the … (more ...)
Sigasi Appoints Dirk Seynhaeve as VP Business Development
Sigasi, the global leader in upfront verification and real-time insight for chip design, is thrilled to welcome Dirk Seynhaeve as Vice President of Business Development. Dirk brings an impressive … (more ...)
Meet Sigasi 5.2!
The Sigasi Studio 5.2 release is live! Improvements For Verilog and SystemVerilog, Sigasi Studio 5.2 reintroduces rename includes many new linting rules improves type checking by adding more contexts … (more ...)
Sigasi Appoints Marc Rummens as VP of Sales
Sigasi, the company that enables hardware engineers to verify their designs upfront, is delighted to bring Marc Rummens on board as VP for Sales. As the semiconductor landscape continues to shift … (more ...)
