AI in RTL Development
AI assistants and agents can generate RTL fast. But in chip design, generated code still has to be reviewed, validated, and understood in full project context before it can move forward.
Sigasi at Chip Development Symposium
After our second conference of the year in the USA, our team is heading for Europe, where we will be present at the Bavarian Chip Design Center (BCDC) Symposium: “Artificial Intelligence in Chip Design.”
Sigasi Visual HDL 2026.1
This release strengthens what matters most in professional FPGA and ASIC development: fast, deterministic, project-aware feedback — even as designs grow larger and workflows evolve.
Survey Results
As Sigasi turns 18, we asked our users a simple question: How are we doing — and what should we improve next? 100’s of respondents took the time to give structured feedback. What we learned reinforces the direction we’re taking.
Sigasi at GOMACTech 2026
After our first conference of the year in India, our team is now heading for New Orleans where we will be present at GOMACTech 2026: “Beyond the Noise” in Government Microelectronics.
18th Birthday
Exactly 18 years ago today, our founders—Hendrik Eeckhaut, PhD in Computer Science Engineering, and Philippe Faes, freshly graduated at the time—launched Sigasi with a single mission: “to make chip design easier and faster”.
Done doesn't mean "correct"
If you’re managing chip projects, the hardest part isn’t writing/generating more RTL; it’s predicting verification + debug. This isn’t an “FPGA problem” or an “ASIC problem.” It’s a verification predictability problem.
The 7 Advantages for (E)CAD Managers
The success of an (E)CAD Manager is measured on predictable delivery and risk reduction. Tooling decisions directly impact productivity, code quality, onboarding speed, and ultimately time-to-market. That’s exactly where Sigasi Visual HDL makes the difference.
Verification is eating the schedule
The 2024 Wilson Research Group Functional Verification Trend Reports point to a harsh reality: design complexity is rising faster than verification capacity, and the industry is paying for it in escapes, respins, and delays.
12,000 Downloads and Counting
It took us more than one year to get to 10,000 downloads. In less than 2 months, 2,000 more downloads were done. Our mission to empower design and verification engineers to save time and costs for their team/company pays off.
Verification Frameworks - Webinar on demand
On January 28th we presented our first webinar in 2026, in which we showed how Sigasi’s shift-left approach saves you valuable time and money in verification. A must watch for design & verification engineers in both SystemVerilog and VHDL.
Google Antigravity meets Sigasi
When Google launched Gemini 3 this week, also Antigravity was launched, an agentic development platform, evolving the IDE into the agent-first era. That got our attention and our VP Operations, Mark Christiaens had a first look at it.
From Pioneers to Navigators
In the heart of Silicon Valley, our VP of Business Development, is paving the way for Sigasi in the ASIC world. When we asked Dirk to introduce our Linting Webinar to the American participants, he came up with his exciting story.
10,000 Downloads and Counting
One year ago, we introduced Sigasi® Visual HDL™ on the VS Code Marketplace. Our goal was clear: empower design and verification engineers to write faster, higher-quality RTL code and save time and costs for their team/company.
Introducing Linting In Chip Design Flow
In complex ASIC and FPGA designs, quality cannot be postponed to simulation. Issues introduced during RTL design cause bloating verification cycles, consuming costly engineering time, and risking expensive silicon re-spins.
