Sigasi Studio has supported Verilog and VHDL languages since 2008, the early knowledge of these languages allowed us to integrate additional SystemVerilog features in the existing tool. SystemVerilog is a rich and complex design language, it is vital for designers to have a tool that understands the design context and gives errors and warnings as they type. We are pleased to be able to provide our customers with this additional language support in the newly released Sigasi Studio 3.5.
As you type, Sigasi Studio marks syntax errors so they can be immediately fixed. By understanding the HDL languages Sigasi Studio can support advanced features such as intelligent auto-completes and code refactoring, making Verilog, VHDL and SystemVerilog design entry easier and more efficient. Integrating SystemVerilog’s preprocessor macros into Sigasi Studio was essential for UVM support and provides the user an easier interface when working with macros in SystemVerilog.
By understanding the design languages, Sigasi Studio is able to instantly check, navigate and offer coding assistance to the SystemVerilog and VHDL designer, enabling the designer to focus on design creation.
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