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What Our Survey Reveals About RTL Quality, Workflow Reality, and AI

Survey Results

As Sigasi turns 18, we asked our users a simple question: How are we doing — and what should we improve next? 100’s of respondents took the time to give structured feedback. What we learned reinforces the direction we’re taking.

Especially around deterministic quality and responsible AI integration we’ve got strong signals. Here are the signals that matter most.

The results

  1. We Are Used Daily — In Real Projects

Sigasi isn’t occasional tooling:

  • almost 60% uses Sigasi every day
  • more than 30% uses uses Sigasi every week

Sigasi isn’t only FPGA:

  • more than 80% uses Sigasi for FPGA design
  • more than 50% uses it in ASIC/SoC or IP design contexts

This tells us something important: Sigasi is embedded in real development workflows — not just experimentation. And those workflows are complex.

  1. Mixed Toolchains Are the Norm

Our users operate in heterogeneous environments:

  • 75% use Siemens ModelSim/Questa
  • 13% use Cadence Xcelium
  • 79% use Git
  • 55% use Jenkins
  • 46% use GitLab CI
  • 37% use OSVVM
  • 44% use VUnit
  • 30% use UVVM
  • 24% use UVM

This confirms what we see in enterprise accounts: There is no single-vendor flow. Design, verification, CI, and lint are layered ecosystems. That’s why our positioning remains consistent: Sigasi does not replace simulation or sign-off. It reduces avoidable churn before those stages.

  1. Deterministic Diagnostics Matter

When we asked about workflow integration:

  • 35% describe Sigasi as “seamless”
  • 62% say it works well with minor scripting

Support satisfaction is also strong:

  • 87% are satisfied or very satisfied

And recommendation scores are high:

  • 76% rated us 8, 9, or 10
  • 26% gave us a 10

This tells us users value reliability and predictability which reinforces our core philosophy: Core diagnostics must be deterministic and reproducible.

In safety, aerospace, automotive, and large ASIC programs, probabilistic (AI) tooling without deterministic validation is not acceptable.

  1. On-the-fly Linting Is Used But It’s Not the Whole Story

Yes, our integrated tools are used often:

  • 77% use our on-the-fly rule checking
  • 81% use autocomplete
  • 72% rely on semantic navigation
  • 51% use live visualizations
  • 38% use safe refactoring

This matters but it’s important to interpret it correctly. Users are not choosing Sigasi because it is “another linter” or replacement for an existing tool. They are using manifestations of a deeper capability: a semantic project model that understands types, scopes, hierarchy, and dependencies across mixed-language projects. Linting is a visible outcome. The semantic engine is foundational.

  1. AI Is Moving Fast — But Determinism Still Wins

Several respondents asked directly about AI capabilities and deployment. Across recent enterprise discussions, we see the same pattern: AI is no longer a curiosity. It is becoming a procurement requirement, but here’s the crucial insight: Teams want AI acceleration without losing deterministic validation.

That’s why our approach is deliberate:

  • AI-assisted coding is optional.
  • The semantic engine remains deterministic.
  • AI-generated RTL is validated in full project context.
  • Diagnostics remain reproducible across teams and CI.

In other words: AI may generate. Sigasi validates.

This is especially important in aerospace, defense, and regulated environments where reproducibility is not optional.

What We’re Doubling Down On

Based on this survey and broader market signals, we are reinforcing three pillars:

  1. Deterministic Engineering Infrastructure

Reducing avoidable churn before integration, simulation, and sign-off.

  1. Mixed-Language Clarity

Supporting real FPGA-to-ASIC transitions and heterogeneous verification frameworks.

  1. Responsible, Enterprise-Ready AI

Optional. Controlled. Guardrailed. Deployment-aware.

Reducing Uncertainty

Tooling in chip design is not about feature lists. It is about reducing uncertainty:

  • Fewer surprises at integration
  • Fewer avoidable review loops
  • Cleaner handoffs to simulation
  • Predictable diagnostics in CI

As complexity continues to increase - and AI enters the workflow - the need for deterministic guardrails only grows. That’s the role we play and intend to play in the future.

Thank you

If you participated in the survey — thank you.

And if you haven’t yet, we’re still listening because the next 18 years of chip design will demand both acceleration and engineering discipline. You can still contribute to the survey before end of month and influence the direction.


2026-02-19, last modified on 2026-02-19