Time to Update!

Say Hi to Sigasi Visual HDL 2024.2

Sigasi Visual HDL 2024.2 Out Now

In May 2024, Sigasi announced a new comprehensive portfolio design to help hardware designers and verification engineers catch specification errors earlier in the chip design cycle and fix the inefficient HDL-based design flow. That portfolio, Sigasi® Visual HDL™ (SVH™), began with the 2024.1 release. Now it’s time for SVH 2024.2.

a screenshot of VHDL 2019 Mode Views in SVH

SVH 2024.2 introduces

  • over a dozen new SystemVerilog linting rules
  • improved Tools and Libraries set up
  • VHDL 2019 Mode Views
  • Smart Indentation
  • vastly improved Autocomplete

Read the full release notes for SVH 2024.2 here  and be sure to update your version!

2024-09-24